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Commit 1726f75b authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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soc: qcom: scm: Add support for AArch32 specific SMC32 calling convention 



Implement the ARM SMC calling convention standard for kernels that run in
Aarch32 mode and need to make SMC32 calls.

Change-Id: Ie8104fc7d9504ca45a6cae1422206c8027b114d1
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent cbc17003

drivers/soc/qcom/scm.c

+42 −5
Original line number Diff line number Diff line
@@ -434,6 +434,7 @@ static int __scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5, 
			  "r" (r5)

			: "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13",

			"x14", "x15", "x16", "x17");



	} while (r0 == SCM_INTERRUPTED);



	if (ret1)
@@ -448,17 +449,53 @@ static int __scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5, 


#else



static int __scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,

static int __scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5,

				u64 *ret1, u64 *ret2, u64 *ret3)

{

	return 0;

	register u32 r0 asm("r0") = w0;

	register u32 r1 asm("r1") = w1;

	register u32 r2 asm("r2") = w2;

	register u32 r3 asm("r3") = w3;

	register u32 r4 asm("r4") = w4;

	register u32 r5 asm("r5") = w5;



	do {

		asm volatile(

			__asmeq("%0", R0_STR)

			__asmeq("%1", R1_STR)

			__asmeq("%2", R2_STR)

			__asmeq("%3", R3_STR)

			__asmeq("%4", R0_STR)

			__asmeq("%5", R1_STR)

			__asmeq("%6", R2_STR)

			__asmeq("%7", R3_STR)

			__asmeq("%8", R4_STR)

			__asmeq("%9", R5_STR)

#ifdef REQUIRES_SEC

			".arch_extension sec\n"

#endif

			"smc	#0\n"

			: "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)

			: "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),

			 "r" (r5));



	} while (r0 == SCM_INTERRUPTED);



	if (ret1)

		*ret1 = r1;

	if (ret2)

		*ret2 = r2;

	if (ret3)

		*ret3 = r3;



	return r0;

}

static int __scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5,



static int __scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,

				u64 *ret1, u64 *ret2, u64 *ret3)

{

	return 0;

}



#endif



struct scm_extra_arg {