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Commit 16eb814e authored by Aparna Das's avatar Aparna Das
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ARM: dts: msm: add register entries for hardware events for plutonium 



Add additional hardware event register entries for plutonium which
enables users to configure these hardware event muxes from sysfs in
order to generate these hardware events.

Change-Id: If3af4ec7434c7bf00741e552d39777c3313fdaa7
Signed-off-by: default avatarAparna Das <adas@codeaurora.org>
parent 707fd824

arch/arm/boot/dts/qcom/msmplutonium-coresight.dtsi

+10 −2
Original line number Diff line number Diff line
@@ -684,14 +684,22 @@ 
		compatible = "qcom,coresight-hwevent";

		reg = <0xfd828018 0x80>,

		      <0xf9112000 0x80>,

		      <0xf9112080 0x4>,

		      <0xf9112084 0x4>,

		      <0xf9112088 0x14>,

		      <0xf9112148 0x38>,

		      <0xfd4ab160 0x80>,

		      <0xfc401600 0x80>,

		      <0xfd4ab360 0x80>,

		      <0xfc596000 0x80>,

		      <0xfc520000 0x4>,

		      <0xfc520058 0x80>,

		      <0xfc528000 0x4>,

		      <0xfc528058 0x80>;

		reg-names = "mmss-mux", "apcs-mux", "ppss-mux", "gcc-mux",

			    "tcsr-mux", "ufs-mux", "pcie0-mux", "pcie1-mux" ;

		reg-names = "mmss-mux", "apcs-hwev", "apcs-spi", "apcs-ppi",

			    "apcs-cpu", "apcs-cci", "ppss-mux", "gcc-mux",

			    "tcsr-mux", "ufs-mux", "pcie0-sysctl", "pcie0-hwev",

			    "pcie1-sysctl", "pcie1-hwev";



		coresight-id = <44>;

		coresight-name = "coresight-hwevent";