Loading drivers/media/platform/msm/camera_v2/sensor/csid/msm_csid.c +30 −2 Original line number Diff line number Diff line Loading @@ -131,7 +131,8 @@ static int msm_csid_config(struct csid_device *csid_dev, struct msm_camera_csid_params *csid_params) { int rc = 0; uint32_t val = 0; uint32_t val = 0, clk_rate = 0, round_rate = 0; struct clk **csid_clk_ptr; void __iomem *csidbase; csidbase = csid_dev->base; if (!csidbase || !csid_params) { Loading @@ -149,6 +150,27 @@ static int msm_csid_config(struct csid_device *csid_dev, msm_csid_reset(csid_dev); csid_clk_ptr = csid_dev->csid_clk; if (!csid_clk_ptr) { pr_err("csi_src_clk get failed\n"); return -EINVAL; } clk_rate = (csid_params->csi_clk > 0) ? (csid_params->csi_clk) : csid_dev->csid_max_clk; round_rate = clk_round_rate(csid_clk_ptr[csid_dev->csid_clk_index], clk_rate); if (round_rate > csid_dev->csid_max_clk) round_rate = csid_dev->csid_max_clk; pr_debug("usr set rate csi_clk clk_rate = %u round_rate = %u\n", clk_rate, round_rate); rc = clk_set_rate(csid_clk_ptr[csid_dev->csid_clk_index], round_rate); if (rc < 0) { pr_err("csi_src_clk set failed\n"); return rc; } val = csid_params->lane_cnt - 1; val |= csid_params->lane_assign << csid_dev->ctrl_reg->csid_reg.csid_dl_input_sel_shift; Loading Loading @@ -785,6 +807,12 @@ static int msm_csid_get_clk_info(struct csid_device *csid_dev, for (i = 0; i < count; i++) { csid_clk_info[i].clk_rate = (rates[i] == 0) ? (long)-1 : rates[i]; if (!strcmp(csid_clk_info[i].clk_name, "csi_src_clk")) { CDBG("%s:%d, copy csi_src_clk", __func__, __LINE__); csid_dev->csid_max_clk = rates[i]; csid_dev->csid_clk_index = i; } CDBG("%s: clk_rate[%d] = %ld\n", __func__, i, csid_clk_info[i].clk_rate); } Loading drivers/media/platform/msm/camera_v2/sensor/csid/msm_csid.h +3 −1 Original line number Diff line number Diff line Loading @@ -85,8 +85,10 @@ struct csid_device { struct csid_ctrl_t *ctrl_reg; uint32_t num_clk; uint32_t num_clk_src_info; struct clk *csid_clk[CSID_NUM_CLK_MAX]; struct regulator *reg_ptr; struct clk *csid_clk[CSID_NUM_CLK_MAX]; uint32_t csid_clk_index; uint32_t csid_max_clk; }; #define VIDIOC_MSM_CSID_RELEASE \ Loading drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c +39 −1 Original line number Diff line number Diff line Loading @@ -48,12 +48,14 @@ static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev, { int rc = 0; int j = 0, curr_lane = 0; uint32_t val = 0; uint32_t val = 0, clk_rate = 0, round_rate = 0; uint8_t lane_cnt = 0; uint16_t lane_mask = 0; void __iomem *csiphybase; uint8_t csiphy_id = csiphy_dev->pdev->id; int32_t lane_val = 0, lane_right = 0, num_lanes = 0; struct clk **csid_phy_clk_ptr; int ratio = 1; csiphybase = csiphy_dev->base; if (!csiphybase) { Loading @@ -70,6 +72,35 @@ static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev, return rc; } csid_phy_clk_ptr = csiphy_dev->csiphy_clk; if (!csid_phy_clk_ptr) { pr_err("csiphy_timer_src_clk get failed\n"); return -EINVAL; } clk_rate = (csiphy_params->csiphy_clk > 0) ? csiphy_params->csiphy_clk : csiphy_dev->csiphy_max_clk; round_rate = clk_round_rate( csid_phy_clk_ptr[csiphy_dev->csiphy_clk_index], clk_rate); if (round_rate >= csiphy_dev->csiphy_max_clk) round_rate = csiphy_dev->csiphy_max_clk; else { ratio = csiphy_dev->csiphy_max_clk/round_rate; csiphy_params->settle_cnt = csiphy_params->settle_cnt/ratio; } CDBG("set from usr csiphy_clk clk_rate = %u round_rate = %u\n", clk_rate, round_rate); rc = clk_set_rate( csid_phy_clk_ptr[csiphy_dev->csiphy_clk_index], round_rate); if (rc < 0) { pr_err("csiphy_timer_src_clk set failed\n"); return rc; } CDBG("%s csiphy_params, mask = 0x%x cnt = %d\n", __func__, csiphy_params->lane_mask, Loading Loading @@ -778,6 +809,13 @@ static int msm_csiphy_get_clk_info(struct csiphy_device *csiphy_dev, for (i = 0; i < count; i++) { csiphy_clk_info[i].clk_rate = (rates[i] == 0) ? (long)-1 : rates[i]; if (!strcmp(csiphy_clk_info[i].clk_name, "csiphy_timer_src_clk")) { CDBG("%s:%d, copy csiphy_timer_src_clk", __func__, __LINE__); csiphy_dev->csiphy_max_clk = rates[i]; csiphy_dev->csiphy_clk_index = i; } CDBG("%s: clk_rate[%d] = %ld\n", __func__, i, csiphy_clk_info[i].clk_rate); } Loading drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h +2 −0 Original line number Diff line number Diff line Loading @@ -82,6 +82,8 @@ struct csiphy_device { int32_t ref_count; uint16_t lane_mask[MAX_CSIPHY]; uint32_t is_3_1_20nm_hw; uint32_t csiphy_clk_index; uint32_t csiphy_max_clk; }; #define VIDIOC_MSM_CSIPHY_RELEASE \ Loading include/media/msm_cam_sensor.h +3 −0 Original line number Diff line number Diff line Loading @@ -179,6 +179,7 @@ struct msm_camera_i2c_read_config { struct msm_camera_csi2_params { struct msm_camera_csid_params csid_params; struct msm_camera_csiphy_params csiphy_params; uint8_t csi_clk_scale_enable; }; struct msm_camera_csi_lane_params { Loading Loading @@ -322,12 +323,14 @@ struct msm_camera_csid_params32 { uint8_t lane_cnt; uint16_t lane_assign; uint8_t phy_sel; uint32_t csi_clk; struct msm_camera_csid_lut_params32 lut_params; }; struct msm_camera_csi2_params32 { struct msm_camera_csid_params32 csid_params; struct msm_camera_csiphy_params csiphy_params; uint8_t csi_clk_scale_enable; }; struct csid_cfg_data32 { Loading Loading
drivers/media/platform/msm/camera_v2/sensor/csid/msm_csid.c +30 −2 Original line number Diff line number Diff line Loading @@ -131,7 +131,8 @@ static int msm_csid_config(struct csid_device *csid_dev, struct msm_camera_csid_params *csid_params) { int rc = 0; uint32_t val = 0; uint32_t val = 0, clk_rate = 0, round_rate = 0; struct clk **csid_clk_ptr; void __iomem *csidbase; csidbase = csid_dev->base; if (!csidbase || !csid_params) { Loading @@ -149,6 +150,27 @@ static int msm_csid_config(struct csid_device *csid_dev, msm_csid_reset(csid_dev); csid_clk_ptr = csid_dev->csid_clk; if (!csid_clk_ptr) { pr_err("csi_src_clk get failed\n"); return -EINVAL; } clk_rate = (csid_params->csi_clk > 0) ? (csid_params->csi_clk) : csid_dev->csid_max_clk; round_rate = clk_round_rate(csid_clk_ptr[csid_dev->csid_clk_index], clk_rate); if (round_rate > csid_dev->csid_max_clk) round_rate = csid_dev->csid_max_clk; pr_debug("usr set rate csi_clk clk_rate = %u round_rate = %u\n", clk_rate, round_rate); rc = clk_set_rate(csid_clk_ptr[csid_dev->csid_clk_index], round_rate); if (rc < 0) { pr_err("csi_src_clk set failed\n"); return rc; } val = csid_params->lane_cnt - 1; val |= csid_params->lane_assign << csid_dev->ctrl_reg->csid_reg.csid_dl_input_sel_shift; Loading Loading @@ -785,6 +807,12 @@ static int msm_csid_get_clk_info(struct csid_device *csid_dev, for (i = 0; i < count; i++) { csid_clk_info[i].clk_rate = (rates[i] == 0) ? (long)-1 : rates[i]; if (!strcmp(csid_clk_info[i].clk_name, "csi_src_clk")) { CDBG("%s:%d, copy csi_src_clk", __func__, __LINE__); csid_dev->csid_max_clk = rates[i]; csid_dev->csid_clk_index = i; } CDBG("%s: clk_rate[%d] = %ld\n", __func__, i, csid_clk_info[i].clk_rate); } Loading
drivers/media/platform/msm/camera_v2/sensor/csid/msm_csid.h +3 −1 Original line number Diff line number Diff line Loading @@ -85,8 +85,10 @@ struct csid_device { struct csid_ctrl_t *ctrl_reg; uint32_t num_clk; uint32_t num_clk_src_info; struct clk *csid_clk[CSID_NUM_CLK_MAX]; struct regulator *reg_ptr; struct clk *csid_clk[CSID_NUM_CLK_MAX]; uint32_t csid_clk_index; uint32_t csid_max_clk; }; #define VIDIOC_MSM_CSID_RELEASE \ Loading
drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c +39 −1 Original line number Diff line number Diff line Loading @@ -48,12 +48,14 @@ static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev, { int rc = 0; int j = 0, curr_lane = 0; uint32_t val = 0; uint32_t val = 0, clk_rate = 0, round_rate = 0; uint8_t lane_cnt = 0; uint16_t lane_mask = 0; void __iomem *csiphybase; uint8_t csiphy_id = csiphy_dev->pdev->id; int32_t lane_val = 0, lane_right = 0, num_lanes = 0; struct clk **csid_phy_clk_ptr; int ratio = 1; csiphybase = csiphy_dev->base; if (!csiphybase) { Loading @@ -70,6 +72,35 @@ static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev, return rc; } csid_phy_clk_ptr = csiphy_dev->csiphy_clk; if (!csid_phy_clk_ptr) { pr_err("csiphy_timer_src_clk get failed\n"); return -EINVAL; } clk_rate = (csiphy_params->csiphy_clk > 0) ? csiphy_params->csiphy_clk : csiphy_dev->csiphy_max_clk; round_rate = clk_round_rate( csid_phy_clk_ptr[csiphy_dev->csiphy_clk_index], clk_rate); if (round_rate >= csiphy_dev->csiphy_max_clk) round_rate = csiphy_dev->csiphy_max_clk; else { ratio = csiphy_dev->csiphy_max_clk/round_rate; csiphy_params->settle_cnt = csiphy_params->settle_cnt/ratio; } CDBG("set from usr csiphy_clk clk_rate = %u round_rate = %u\n", clk_rate, round_rate); rc = clk_set_rate( csid_phy_clk_ptr[csiphy_dev->csiphy_clk_index], round_rate); if (rc < 0) { pr_err("csiphy_timer_src_clk set failed\n"); return rc; } CDBG("%s csiphy_params, mask = 0x%x cnt = %d\n", __func__, csiphy_params->lane_mask, Loading Loading @@ -778,6 +809,13 @@ static int msm_csiphy_get_clk_info(struct csiphy_device *csiphy_dev, for (i = 0; i < count; i++) { csiphy_clk_info[i].clk_rate = (rates[i] == 0) ? (long)-1 : rates[i]; if (!strcmp(csiphy_clk_info[i].clk_name, "csiphy_timer_src_clk")) { CDBG("%s:%d, copy csiphy_timer_src_clk", __func__, __LINE__); csiphy_dev->csiphy_max_clk = rates[i]; csiphy_dev->csiphy_clk_index = i; } CDBG("%s: clk_rate[%d] = %ld\n", __func__, i, csiphy_clk_info[i].clk_rate); } Loading
drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h +2 −0 Original line number Diff line number Diff line Loading @@ -82,6 +82,8 @@ struct csiphy_device { int32_t ref_count; uint16_t lane_mask[MAX_CSIPHY]; uint32_t is_3_1_20nm_hw; uint32_t csiphy_clk_index; uint32_t csiphy_max_clk; }; #define VIDIOC_MSM_CSIPHY_RELEASE \ Loading
include/media/msm_cam_sensor.h +3 −0 Original line number Diff line number Diff line Loading @@ -179,6 +179,7 @@ struct msm_camera_i2c_read_config { struct msm_camera_csi2_params { struct msm_camera_csid_params csid_params; struct msm_camera_csiphy_params csiphy_params; uint8_t csi_clk_scale_enable; }; struct msm_camera_csi_lane_params { Loading Loading @@ -322,12 +323,14 @@ struct msm_camera_csid_params32 { uint8_t lane_cnt; uint16_t lane_assign; uint8_t phy_sel; uint32_t csi_clk; struct msm_camera_csid_lut_params32 lut_params; }; struct msm_camera_csi2_params32 { struct msm_camera_csid_params32 csid_params; struct msm_camera_csiphy_params csiphy_params; uint8_t csi_clk_scale_enable; }; struct csid_cfg_data32 { Loading