Commit 163fc089 authored Nov 04, 2014 by Sahitya Tummala

ARM: dts: msm: Modify SDHC2 clock rate for msm8939



Reduce SDHC2 clock rate to 177MHz to avoid data CRC errors
observed on SDR104 cards at 200MHz.

Change-Id: I5829bc267acdff77aca7930afb75670992f867ce
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>

parent dbd2b72e

arch/arm/boot/dts/qcom/msm8939-common.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -1100,7 +1100,7 @@
		<&clock_gcc clk_gcc_sdcc2_apps_clk>;
		clock-names = "iface_clk", "core_clk";

		qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
		qcom,clk-rates = <400000 25000000 50000000 100000000 177770000>;

		status = "disabled";
		};