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Commit 15e4db7b authored by Ben Dooks's avatar Ben Dooks Committed by Russell King
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[ARM] 4219/1: S3C2443: DMA source definitions 



Defines for the S3C2443 DMA source selection,
and update the maximum channels to 6 if the S3C2443
is selected.

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 64f33bea

include/asm-arm/arch-s3c2410/dma.h

+35 −1
Original line number Original line Diff line number Diff line
@@ -51,13 +51,19 @@ enum dma_ch { 
	DMACH_UART0_SRC2,	/* s3c2412 second uart sources */

	DMACH_UART0_SRC2,	/* s3c2412 second uart sources */

	DMACH_UART1_SRC2,

	DMACH_UART1_SRC2,

	DMACH_UART2_SRC2,

	DMACH_UART2_SRC2,

	DMACH_UART3,		/* s3c2443 has extra uart */

	DMACH_UART3_SRC2,

	DMACH_MAX,		/* the end entry */

	DMACH_MAX,		/* the end entry */

};

};





#define DMACH_LOW_LEVEL	(1<<28)	/* use this to specifiy hardware ch no */

#define DMACH_LOW_LEVEL	(1<<28)	/* use this to specifiy hardware ch no */





/* we have 4 dma channels */

/* we have 4 dma channels */

#ifndef CONFIG_CPU_S3C2443

#define S3C2410_DMA_CHANNELS		(4)

#define S3C2410_DMA_CHANNELS		(4)

#else

#define S3C2410_DMA_CHANNELS		(6)

#endif





/* types */

/* types */
@@ -321,6 +327,7 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn); 
#define S3C2410_DMA_DCDST       (0x1C)

#define S3C2410_DMA_DCDST       (0x1C)

#define S3C2410_DMA_DMASKTRIG   (0x20)

#define S3C2410_DMA_DMASKTRIG   (0x20)

#define S3C2412_DMA_DMAREQSEL	(0x24)

#define S3C2412_DMA_DMAREQSEL	(0x24)

#define S3C2443_DMA_DMAREQSEL	(0x24)





#define S3C2410_DISRCC_INC	(1<<0)

#define S3C2410_DISRCC_INC	(1<<0)

#define S3C2410_DISRCC_APB	(1<<1)

#define S3C2410_DISRCC_APB	(1<<1)
@@ -415,4 +422,31 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn); 
#define S3C2412_DMAREQSEL_UART2_1	S3C2412_DMAREQSEL_SRC(24)

#define S3C2412_DMAREQSEL_UART2_1	S3C2412_DMAREQSEL_SRC(24)





#endif

#endif



#define S3C2443_DMAREQSEL_SRC(x)	((x)<<1)



#define S3C2443_DMAREQSEL_HW		(1)



#define S3C2443_DMAREQSEL_SPI0TX	S3C2443_DMAREQSEL_SRC(0)

#define S3C2443_DMAREQSEL_SPI0RX	S3C2443_DMAREQSEL_SRC(1)

#define S3C2443_DMAREQSEL_SPI1TX	S3C2443_DMAREQSEL_SRC(2)

#define S3C2443_DMAREQSEL_SPI1RX	S3C2443_DMAREQSEL_SRC(3)

#define S3C2443_DMAREQSEL_I2STX		S3C2443_DMAREQSEL_SRC(4)

#define S3C2443_DMAREQSEL_I2SRX		S3C2443_DMAREQSEL_SRC(5)

#define S3C2443_DMAREQSEL_TIMER		S3C2443_DMAREQSEL_SRC(9)

#define S3C2443_DMAREQSEL_SDI		S3C2443_DMAREQSEL_SRC(10)

#define S3C2443_DMAREQSEL_XDREQ0	S3C2443_DMAREQSEL_SRC(17)

#define S3C2443_DMAREQSEL_XDREQ1	S3C2443_DMAREQSEL_SRC(18)

#define S3C2443_DMAREQSEL_UART0_0	S3C2443_DMAREQSEL_SRC(19)

#define S3C2443_DMAREQSEL_UART0_1	S3C2443_DMAREQSEL_SRC(20)

#define S3C2443_DMAREQSEL_UART1_0	S3C2443_DMAREQSEL_SRC(21)

#define S3C2443_DMAREQSEL_UART1_1	S3C2443_DMAREQSEL_SRC(22)

#define S3C2443_DMAREQSEL_UART2_0	S3C2443_DMAREQSEL_SRC(23)

#define S3C2443_DMAREQSEL_UART2_1	S3C2443_DMAREQSEL_SRC(24)

#define S3C2443_DMAREQSEL_UART3_0	S3C2443_DMAREQSEL_SRC(25)

#define S3C2443_DMAREQSEL_UART3_1	S3C2443_DMAREQSEL_SRC(26)

#define S3C2443_DMAREQSEL_PCMOUT	S3C2443_DMAREQSEL_SRC(27)

#define S3C2443_DMAREQSEL_PCMIN 	S3C2443_DMAREQSEL_SRC(28)

#define S3C2443_DMAREQSEL_MICIN		S3C2443_DMAREQSEL_SRC(29)



#endif /* __ASM_ARCH_DMA_H */
 
#endif /* __ASM_ARCH_DMA_H */