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Commit 14ed4539 authored by Casey Piper's avatar Casey Piper
Browse files

clk: qcom: mdss: add support for HDMI autopll calculations 



Automatically calculate the register
values needed for HDMI PLL based on the
pixel clock.

Change-Id: I6fbe519e0316c3f9cc12cd0afd5aa08a90deed7d
Signed-off-by: default avatarCasey Piper <cpiper@codeaurora.org>
parent bba41e29

drivers/clk/qcom/mdss/mdss-hdmi-pll-20nm.c

+156 −424

File changed.

Preview size limit exceeded, changes collapsed.

drivers/clk/qcom/mdss/mdss-hdmi-pll.h

+10 −0
Original line number Diff line number Diff line
@@ -13,11 +13,21 @@ 
#ifndef __MDSS_HDMI_PLL_H

#define __MDSS_HDMI_PLL_H



struct hdmi_pll_cfg {

	unsigned long vco_rate;

	u32 reg;

};



struct hdmi_pll_vco_clk {

	unsigned long	rate;	/* current vco rate */

	unsigned long	min_rate;	/* min vco rate */

	unsigned long	max_rate;	/* max vco rate */

	bool		rate_set;

	struct hdmi_pll_cfg *ip_seti;

	struct hdmi_pll_cfg *cp_seti;

	struct hdmi_pll_cfg *ip_setp;

	struct hdmi_pll_cfg *cp_setp;

	struct hdmi_pll_cfg *crctrl;

	void		*priv;



	struct clk	c;