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Commit 1428ea92 authored by Hemant Kumar's avatar Hemant Kumar
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usb: dwc3: Clear DELAYP1TRANS bit in DWC3_GUSB3PIPECTL(0) reg 



Hardware programming guide recommends to clear DELAYP1TRANS bit
as part of phy soft reset sequence. This bit is set to 1
incorrectly.

Change-Id: I47d5eea1f342c8e88b799ec9816903911bd5ff98
Signed-off-by: default avatarHemant Kumar <hemantk@codeaurora.org>
parent d9c0d608

drivers/usb/dwc3/core.c

+3 −5
Original line number Diff line number Diff line
@@ -160,11 +160,9 @@ static void dwc3_core_and_phy_soft_reset(struct dwc3 *dwc) 
	reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;

	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);



	if (dwc->revision >= DWC3_REVISION_270A) {

	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));

		reg |= DWC3_GUSB3PIPECTL_DELAYP1TRANS;

	reg &= ~DWC3_GUSB3PIPECTL_DELAYP1TRANS;

	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

	}



	/* Assert USB2 PHY reset */

	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));