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Commit 138ee960 authored by Sebastian Hesselbarth's avatar Sebastian Hesselbarth Committed by Jason Cooper
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ARM: dove: Restructure SoC device tree descriptor 



This patch adds proper ranges for all mapped addresses within
dove SoC and moves the interrupt controller node inside the simple-bus
node.

Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 3fbcd3d0

arch/arm/boot/dts/dove.dtsi

+18 −12
Original line number Diff line number Diff line
@@ -4,27 +4,33 @@ 
	compatible = "marvell,dove";

	model = "Marvell Armada 88AP510 SoC";



	interrupt-parent = <&intc>;



	intc: interrupt-controller {

		compatible = "marvell,orion-intc";

		interrupt-controller;

		#interrupt-cells = <1>;

		reg = <0xf1020204 0x04>,

		      <0xf1020214 0x04>;

	};



	mbus@f1000000 {

	soc@f1000000 {

		compatible = "simple-bus";

		ranges = <0 0xf1000000 0x4000000>;

		#address-cells = <1>;

		#size-cells = <1>;

		interrupt-parent = <&intc>;



		ranges = <0xc8000000 0xc8000000 0x0100000   /* CESA SRAM   1M */

		          0xe0000000 0xe0000000 0x8000000   /* PCIe0 Mem 128M */

		          0xe8000000 0xe8000000 0x8000000   /* PCIe1 Mem 128M */

		          0xf0000000 0xf0000000 0x0100000   /* ScratchPad  1M */

		          0x00000000 0xf1000000 0x1000000   /* SB/NB regs 16M */

		          0xf2000000 0xf2000000 0x0100000   /* PCIe0 I/O   1M */

		          0xf2100000 0xf2100000 0x0100000   /* PCIe0 I/O   1M */

		          0xf8000000 0xf8000000 0x8000000>; /* BootROM   128M */



		l2: l2-cache {

			compatible = "marvell,tauros2-cache";

			marvell,tauros2-cache-features = <0>;

		};



		intc: interrupt-controller {

			compatible = "marvell,orion-intc";

			interrupt-controller;

			#interrupt-cells = <1>;

			reg = <0x20204 0x04>, <0x20214 0x04>;

		};



		uart0: serial@12000 {

			compatible = "ns16550a";

			reg = <0x12000 0x100>;