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Commit 124e13db authored by Xiaogang Cui's avatar Xiaogang Cui
Browse files

ARM: dts: msm: add coresight etm components for 8936 



Add device tree entries for CoreSight ETM components which are necessary to
enable processor trace.

Change-Id: I73353db9613d444d264e7c8abc4446129aa43752
Signed-off-by: default avatarXiaogang Cui <xiaogang@codeaurora.org>
parent 3c7ef256

arch/arm/boot/dts/qcom/msm8936-coresight.dtsi

+119 −25
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
		interrupt-names = "byte-cntr-irq";



		qcom,memory-size = <0x100000>;

		qcom,tmc-flush-powerdown;



		coresight-id = <0>;

		coresight-name = "coresight-tmc-etr";
@@ -93,6 +94,8 @@ 
		coresight-default-sink;

		coresight-ctis = <&cti0 &cti8>;



		qcom,tmc-flush-powerdown;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";
@@ -149,13 +152,104 @@ 
		clock-names = "core_clk", "core_a_clk";

	};



	funnel_apss: funnel@8e1000 {

		compatible = "arm,coresight-funnel";

		reg = <0x8e1000 0x1000>;

		reg-names = "funnel-base";



		coresight-id = <7>;

		coresight-name = "coresight-funnel-apss";

		coresight-nr-inports = <8>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <4>;



		qcom,funnel-save-restore;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm0: etm@8fc000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x8fc000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <8>;

		coresight-name = "coresight-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <4>;

		coresight-etm-cpu = <&CPU0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm1: etm@8fd000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x8fd000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <9>;

		coresight-name = "coresight-etm1";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <5>;

		coresight-etm-cpu = <&CPU1>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm2: etm@8fe000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x8fe000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <10>;

		coresight-name = "coresight-etm2";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <6>;

		coresight-etm-cpu = <&CPU2>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm3: etm@8ff000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x8ff000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <11>;

		coresight-name = "coresight-etm3";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <7>;

		coresight-etm-cpu = <&CPU3>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	stm: stm@802000 {

		compatible = "arm,coresight-stm";

		reg = <0x802000 0x1000>,

		      <0x9280000 0x180000>;

		reg-names = "stm-base", "stm-data-base";



		coresight-id = <7>;

		coresight-id = <12>;

		coresight-name = "coresight-stm";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;
@@ -172,7 +266,7 @@ 
		reg = <0x801000 0x1000>;

		reg-names = "csr-base";



		coresight-id = <8>;

		coresight-id = <13>;

		coresight-name = "coresight-csr";

		coresight-nr-inports = <0>;

		qcom,blk-size = <1>;
@@ -183,7 +277,7 @@ 
		reg = <0x810000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <9>;

		coresight-id = <14>;

		coresight-name = "coresight-cti0";

		coresight-nr-inports = <0>;
@@ -197,7 +291,7 @@ 
		reg = <0x811000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <10>;

		coresight-id = <15>;

		coresight-name = "coresight-cti1";

		coresight-nr-inports = <0>;
@@ -211,7 +305,7 @@ 
		reg = <0x812000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <11>;

		coresight-id = <16>;

		coresight-name = "coresight-cti2";

		coresight-nr-inports = <0>;
@@ -225,7 +319,7 @@ 
		reg = <0x813000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <12>;

		coresight-id = <17>;

		coresight-name = "coresight-cti3";

		coresight-nr-inports = <0>;
@@ -239,7 +333,7 @@ 
		reg = <0x814000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <13>;

		coresight-id = <18>;

		coresight-name = "coresight-cti4";

		coresight-nr-inports = <0>;
@@ -253,7 +347,7 @@ 
		reg = <0x815000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <14>;

		coresight-id = <19>;

		coresight-name = "coresight-cti5";

		coresight-nr-inports = <0>;
@@ -267,7 +361,7 @@ 
		reg = <0x816000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <15>;

		coresight-id = <20>;

		coresight-name = "coresight-cti6";

		coresight-nr-inports = <0>;
@@ -281,7 +375,7 @@ 
		reg = <0x817000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <16>;

		coresight-id = <21>;

		coresight-name = "coresight-cti7";

		coresight-nr-inports = <0>;
@@ -295,7 +389,7 @@ 
		reg = <0x818000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <17>;

		coresight-id = <22>;

		coresight-name = "coresight-cti8";

		coresight-nr-inports = <0>;
@@ -309,7 +403,7 @@ 
		reg = <0x8f8000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <18>;

		coresight-id = <23>;

		coresight-name = "coresight-cti-cpu0";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU0>;
@@ -325,7 +419,7 @@ 
		reg = <0x8f9000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <19>;

		coresight-id = <24>;

		coresight-name = "coresight-cti-cpu1";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU1>;
@@ -341,7 +435,7 @@ 
		reg = <0x8fa000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <20>;

		coresight-id = <25>;

		coresight-name = "coresight-cti-cpu2";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU2>;
@@ -357,7 +451,7 @@ 
		reg = <0x8fb000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <21>;

		coresight-id = <26>;

		coresight-name = "coresight-cti-cpu3";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU3>;
@@ -373,7 +467,7 @@ 
		reg = <0x83c000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <22>;

		coresight-id = <27>;

		coresight-name = "coresight-cti-rpm-cpu0";

		coresight-nr-inports = <0>;
@@ -387,7 +481,7 @@ 
		reg = <0x838000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <23>;

		coresight-id = <28>;

		coresight-name = "coresight-cti-modem-cpu0";

		coresight-nr-inports = <0>;
@@ -401,7 +495,7 @@ 
		reg = <0x835000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <24>;

		coresight-id = <29>;

		coresight-name = "coresight-cti-wcn-cpu0";

		coresight-nr-inports = <0>;
@@ -415,7 +509,7 @@ 
		reg = <0x830000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <25>;

		coresight-id = <30>;

		coresight-name = "coresight-cti-video-cpu0";

		coresight-nr-inports = <0>;
@@ -427,7 +521,7 @@ 
	rpm_etm0 {

		compatible = "qcom,coresight-rpm-etm";



		coresight-id = <26>;

		coresight-id = <31>;

		coresight-name = "coresight-rpm-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;
@@ -438,7 +532,7 @@ 
	wcn_etm0 {

		compatible = "qcom,coresight-wcn-etm";



		coresight-id = <27>;

		coresight-id = <32>;

		coresight-name = "coresight-wcn-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;
@@ -449,7 +543,7 @@ 
	modem_etm0 {

		compatible = "qcom,coresight-modem-etm";



		coresight-id = <28>;

		coresight-id = <33>;

		coresight-name = "coresight-modem-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;
@@ -464,7 +558,7 @@ 
		      <0x5e00c 0x4>;

		reg-names = "fuse-base", "nidnt-fuse-base", "qpdi-fuse-base";



		coresight-id = <29>;

		coresight-id = <34>;

		coresight-name = "coresight-fuse";

		coresight-nr-inports = <0>;

	};
@@ -478,7 +572,7 @@ 
		      <0x7885010 0x4>;

		reg-names = "wrapper-mux", "wrapper-lockaccess", "spmi-mux",

		            "usbbam-mux", "blsp-mux";

		coresight-id = <30>;

		coresight-id = <35>;

		coresight-name = "coresight-hwevent";

		coresight-nr-inports = <0>;
@@ -492,7 +586,7 @@ 
		reg = <0x1941000 0x4>;

		reg-names = "qpdi-base";



		coresight-id = <31>;

		coresight-id = <36>;

		coresight-name = "coresight-qpdi";

		coresight-nr-inports = <0>;