Merge "Revert "power: qpnp-fg: disable ESR measurements during sleep"" (1060efab) · Commits · e / devices / android_kernel_sony_msm8994

drivers/power/qpnp-fg.c

+20 −88

Original line number	Original line	Diff line number	Diff line
	@@ -56,7 +56,6 @@
	#define OTP_CFG1 0xE2		#define OTP_CFG1 0xE2
	#define SOC_BOOT_MOD 0x50		#define SOC_BOOT_MOD 0x50
	#define SOC_RESTART 0x51		#define SOC_RESTART 0x51
	#define ESR_MEAS_EN 0xF5

	#define REG_OFFSET_PERP_SUBTYPE 0x05		#define REG_OFFSET_PERP_SUBTYPE 0x05

	@@ -235,7 +234,6 @@ struct fg_chip {
	struct work_struct batt_profile_init;		struct work_struct batt_profile_init;
	struct work_struct dump_sram;		struct work_struct dump_sram;
	struct power_supply *batt_psy;		struct power_supply *batt_psy;
	spinlock_t sec_access_lock;
	bool profile_loaded;		bool profile_loaded;
	bool use_otp_profile;		bool use_otp_profile;
	bool battery_missing;		bool battery_missing;
	@@ -328,7 +326,7 @@ static void fill_string(char str, size_t str_len, u8 buf, int buf_len)
	}		}
	}		}

	static int fg_write_raw(struct fg_chip chip, u8 val, u16 addr, int len)		static int fg_write(struct fg_chip chip, u8 val, u16 addr, int len)
	{		{
	int rc = 0;		int rc = 0;
	struct spmi_device *spmi = chip->spmi;		struct spmi_device *spmi = chip->spmi;
	@@ -386,13 +384,13 @@ static int fg_read(struct fg_chip chip, u8 val, u16 addr, int len)
	return rc;		return rc;
	}		}

	static int fg_masked_write_raw(struct fg_chip *chip, u16 addr,		static int fg_masked_write(struct fg_chip *chip, u16 addr,
	u8 mask, u8 val)		u8 mask, u8 val, int len)
	{		{
	int rc;		int rc;
	u8 reg;		u8 reg;

	rc = fg_read(chip, &reg, addr, 1);		rc = fg_read(chip, &reg, addr, len);
	if (rc) {		if (rc) {
	pr_err("spmi read failed: addr=%03X, rc=%d\n", addr, rc);		pr_err("spmi read failed: addr=%03X, rc=%d\n", addr, rc);
	return rc;		return rc;
	@@ -404,7 +402,7 @@ static int fg_masked_write_raw(struct fg_chip *chip, u16 addr,

	pr_debug("Writing 0x%x\n", reg);		pr_debug("Writing 0x%x\n", reg);

	rc = fg_write_raw(chip, &reg, addr, 1);		rc = fg_write(chip, &reg, addr, len);
	if (rc) {		if (rc) {
	pr_err("spmi write failed: addr=%03X, rc=%d\n", addr, rc);		pr_err("spmi write failed: addr=%03X, rc=%d\n", addr, rc);
	return rc;		return rc;
	@@ -413,60 +411,6 @@ static int fg_masked_write_raw(struct fg_chip *chip, u16 addr,
	return rc;		return rc;
	}		}

	static int fg_write(struct fg_chip chip, u8 val, u16 addr, int len)
	{
	unsigned long flags;
	int rc;

	spin_lock_irqsave(&chip->sec_access_lock, flags);
	rc = fg_write_raw(chip, val, addr, len);
	spin_unlock_irqrestore(&chip->sec_access_lock, flags);
	return rc;
	}

	static int fg_masked_write(struct fg_chip *chip, u16 addr,
	u8 mask, u8 val)
	{
	unsigned long flags;
	int rc;

	spin_lock_irqsave(&chip->sec_access_lock, flags);
	rc = fg_masked_write_raw(chip, addr, mask, val);
	spin_unlock_irqrestore(&chip->sec_access_lock, flags);
	return rc;
	}

	/*
	* Unlocks sec access and writes to the register specified.
	*
	* This function holds a spin lock to exclude other register writes while
	* the two writes are taking place.
	*/
	#define SEC_ACCESS_OFFSET 0xD0
	#define SEC_ACCESS_VALUE 0xA5
	#define PERIPHERAL_MASK 0xFF
	static int fg_sec_masked_write(struct fg_chip *chip, u16 base, u8 mask, u8 val)
	{
	unsigned long flags;
	int rc;
	u16 peripheral_base = base & (~PERIPHERAL_MASK);

	spin_lock_irqsave(&chip->sec_access_lock, flags);

	rc = fg_masked_write_raw(chip, peripheral_base + SEC_ACCESS_OFFSET,
	SEC_ACCESS_VALUE, SEC_ACCESS_VALUE);
	if (rc) {
	dev_err(chip->dev, "Unable to unlock sec_access: %d", rc);
	goto out;
	}

	rc = fg_masked_write_raw(chip, base, mask, val);

	out:
	spin_unlock_irqrestore(&chip->sec_access_lock, flags);
	return rc;
	}

	#define RIF_MEM_ACCESS_REQ BIT(7)		#define RIF_MEM_ACCESS_REQ BIT(7)
	static inline bool fg_check_sram_access(struct fg_chip *chip)		static inline bool fg_check_sram_access(struct fg_chip *chip)
	{		{
	@@ -536,7 +480,7 @@ static int fg_config_access(struct fg_chip *chip, bool write,
	if (otp) {		if (otp) {
	/* Configure OTP access */		/* Configure OTP access */
	rc = fg_masked_write(chip, chip->mem_base + OTP_CFG1,		rc = fg_masked_write(chip, chip->mem_base + OTP_CFG1,
	0xFF, 0x00);		0xFF, 0x00, 1);
	if (rc) {		if (rc) {
	pr_err("failed to set OTP cfg\n");		pr_err("failed to set OTP cfg\n");
	return -EIO;		return -EIO;
	@@ -561,7 +505,7 @@ static int fg_req_and_wait_access(struct fg_chip *chip, int timeout)

	if (!fg_check_sram_access(chip)) {		if (!fg_check_sram_access(chip)) {
	rc = fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,		rc = fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,
	RIF_MEM_ACCESS_REQ, RIF_MEM_ACCESS_REQ);		RIF_MEM_ACCESS_REQ, RIF_MEM_ACCESS_REQ, 1);
	if (rc) {		if (rc) {
	pr_err("failed to set mem access bit\n");		pr_err("failed to set mem access bit\n");
	return -EIO;		return -EIO;
	@@ -590,7 +534,7 @@ static void fg_release_access_if_necessary(struct fg_chip *chip)
	mutex_lock(&chip->rw_lock);		mutex_lock(&chip->rw_lock);
	if (atomic_sub_return(1, &chip->memif_user_cnt) <= 0) {		if (atomic_sub_return(1, &chip->memif_user_cnt) <= 0) {
	fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,		fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,
	RIF_MEM_ACCESS_REQ, 0);		RIF_MEM_ACCESS_REQ, 0, 1);
	INIT_COMPLETION(chip->sram_access);		INIT_COMPLETION(chip->sram_access);
	}		}
	mutex_unlock(&chip->rw_lock);		mutex_unlock(&chip->rw_lock);
	@@ -695,7 +639,7 @@ out:

	if (!keep_access && (user_cnt == 0) && !rc) {		if (!keep_access && (user_cnt == 0) && !rc) {
	rc = fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,		rc = fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,
	RIF_MEM_ACCESS_REQ, 0);		RIF_MEM_ACCESS_REQ, 0, 1);
	if (rc)		if (rc)
	pr_err("failed to set mem access bit\n");		pr_err("failed to set mem access bit\n");
	INIT_COMPLETION(chip->sram_access);		INIT_COMPLETION(chip->sram_access);
	@@ -779,7 +723,7 @@ out:

	if (!keep_access && (user_cnt == 0) && !rc) {		if (!keep_access && (user_cnt == 0) && !rc) {
	rc = fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,		rc = fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,
	RIF_MEM_ACCESS_REQ, 0);		RIF_MEM_ACCESS_REQ, 0, 1);
	if (rc) {		if (rc) {
	pr_err("failed to set mem access bit\n");		pr_err("failed to set mem access bit\n");
	rc = -EIO;		rc = -EIO;
	@@ -1529,11 +1473,11 @@ wait:
	*/		*/
	mutex_lock(&chip->rw_lock);		mutex_lock(&chip->rw_lock);
	fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,		fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,
	RIF_MEM_ACCESS_REQ, 0);		RIF_MEM_ACCESS_REQ, 0, 1);
	INIT_COMPLETION(chip->sram_access);		INIT_COMPLETION(chip->sram_access);

	rc = fg_masked_write(chip, chip->soc_base + SOC_BOOT_MOD,		rc = fg_masked_write(chip, chip->soc_base + SOC_BOOT_MOD,
	NO_OTP_PROF_RELOAD, 0);		NO_OTP_PROF_RELOAD, 0, 1);
	if (rc) {		if (rc) {
	pr_err("failed to set no otp reload bit\n");		pr_err("failed to set no otp reload bit\n");
	goto unlock_and_fail;		goto unlock_and_fail;
	@@ -1542,14 +1486,14 @@ wait:
	/* unset the restart bits so the fg doesn't continuously restart */		/* unset the restart bits so the fg doesn't continuously restart */
	reg = REDO_FIRST_ESTIMATE \| RESTART_GO;		reg = REDO_FIRST_ESTIMATE \| RESTART_GO;
	rc = fg_masked_write(chip, chip->soc_base + SOC_RESTART,		rc = fg_masked_write(chip, chip->soc_base + SOC_RESTART,
	reg, 0);		reg, 0, 1);
	if (rc) {		if (rc) {
	pr_err("failed to unset fg restart: %d\n", rc);		pr_err("failed to unset fg restart: %d\n", rc);
	goto unlock_and_fail;		goto unlock_and_fail;
	}		}

	rc = fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,		rc = fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,
	LOW_LATENCY, LOW_LATENCY);		LOW_LATENCY, LOW_LATENCY, 1);
	if (rc) {		if (rc) {
	pr_err("failed to set low latency access bit\n");		pr_err("failed to set low latency access bit\n");
	goto unlock_and_fail;		goto unlock_and_fail;
	@@ -1572,10 +1516,10 @@ wait:

	mutex_lock(&chip->rw_lock);		mutex_lock(&chip->rw_lock);
	fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,		fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,
	RIF_MEM_ACCESS_REQ, 0);		RIF_MEM_ACCESS_REQ, 0, 1);
	INIT_COMPLETION(chip->sram_access);		INIT_COMPLETION(chip->sram_access);
	rc = fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,		rc = fg_masked_write(chip, chip->mem_base + MEM_INTF_CFG,
	LOW_LATENCY, 0);		LOW_LATENCY, 0, 1);
	if (rc) {		if (rc) {
	pr_err("failed to set low latency access bit\n");		pr_err("failed to set low latency access bit\n");
	goto unlock_and_fail;		goto unlock_and_fail;
	@@ -1607,7 +1551,7 @@ wait:
	* the profile		* the profile
	*/		*/
	rc = fg_masked_write(chip, chip->soc_base + SOC_BOOT_MOD,		rc = fg_masked_write(chip, chip->soc_base + SOC_BOOT_MOD,
	NO_OTP_PROF_RELOAD, NO_OTP_PROF_RELOAD);		NO_OTP_PROF_RELOAD, NO_OTP_PROF_RELOAD, 1);
	if (rc) {		if (rc) {
	pr_err("failed to set no otp reload bit\n");		pr_err("failed to set no otp reload bit\n");
	goto fail;		goto fail;
	@@ -1615,7 +1559,7 @@ wait:

	reg = REDO_FIRST_ESTIMATE \| RESTART_GO;		reg = REDO_FIRST_ESTIMATE \| RESTART_GO;
	rc = fg_masked_write(chip, chip->soc_base + SOC_RESTART,		rc = fg_masked_write(chip, chip->soc_base + SOC_RESTART,
	reg, reg);		reg, reg, 1);
	if (rc) {		if (rc) {
	pr_err("failed to set fg restart: %d\n", rc);		pr_err("failed to set fg restart: %d\n", rc);
	goto fail;		goto fail;
	@@ -1640,7 +1584,7 @@ wait:
	pr_err("Battery profile reloading failed, no first estimate\n");		pr_err("Battery profile reloading failed, no first estimate\n");

	rc = fg_masked_write(chip, chip->soc_base + SOC_BOOT_MOD,		rc = fg_masked_write(chip, chip->soc_base + SOC_BOOT_MOD,
	NO_OTP_PROF_RELOAD, 0);		NO_OTP_PROF_RELOAD, 0, 1);
	if (rc) {		if (rc) {
	pr_err("failed to set no otp reload bit\n");		pr_err("failed to set no otp reload bit\n");
	goto fail;		goto fail;
	@@ -1648,7 +1592,7 @@ wait:
	/* unset the restart bits so the fg doesn't continuously restart */		/* unset the restart bits so the fg doesn't continuously restart */
	reg = REDO_FIRST_ESTIMATE \| RESTART_GO;		reg = REDO_FIRST_ESTIMATE \| RESTART_GO;
	rc = fg_masked_write(chip, chip->soc_base + SOC_RESTART,		rc = fg_masked_write(chip, chip->soc_base + SOC_RESTART,
	reg, 0);		reg, 0, 1);
	if (rc) {		if (rc) {
	pr_err("failed to unset fg restart: %d\n", rc);		pr_err("failed to unset fg restart: %d\n", rc);
	goto fail;		goto fail;
	@@ -2407,7 +2351,6 @@ static int fg_probe(struct spmi_device *spmi)
	chip->dev = &(spmi->dev);		chip->dev = &(spmi->dev);

	mutex_init(&chip->rw_lock);		mutex_init(&chip->rw_lock);
	spin_lock_init(&chip->sec_access_lock);
	INIT_DELAYED_WORK(&chip->update_jeita_setting,		INIT_DELAYED_WORK(&chip->update_jeita_setting,
	update_jeita_setting);		update_jeita_setting);
	INIT_DELAYED_WORK(&chip->update_sram_data, update_sram_data);		INIT_DELAYED_WORK(&chip->update_sram_data, update_sram_data);
	@@ -2548,7 +2491,6 @@ of_init_fail:
	return rc;		return rc;
	}		}

	#define ESR_MEAS_EN_BIT BIT(0)
	static int fg_suspend(struct device *dev)		static int fg_suspend(struct device *dev)
	{		{
	struct fg_chip *chip = dev_get_drvdata(dev);		struct fg_chip *chip = dev_get_drvdata(dev);
	@@ -2571,11 +2513,6 @@ static int fg_suspend(struct device *dev)
	if ((total_time_ms > 1500) && (fg_debug_mask & FG_STATUS))		if ((total_time_ms > 1500) && (fg_debug_mask & FG_STATUS))
	pr_info("spent %dms configuring rbias\n", total_time_ms);		pr_info("spent %dms configuring rbias\n", total_time_ms);

	rc = fg_sec_masked_write(chip, chip->batt_base + ESR_MEAS_EN,
	ESR_MEAS_EN_BIT, 0);
	if (rc)
	pr_err("Unable to disable ESR measurements\n");

	return 0;		return 0;
	}		}

	@@ -2601,11 +2538,6 @@ static int fg_resume(struct device *dev)
	if ((total_time_ms > 1500) && (fg_debug_mask & FG_STATUS))		if ((total_time_ms > 1500) && (fg_debug_mask & FG_STATUS))
	pr_info("spent %dms configuring rbias\n", total_time_ms);		pr_info("spent %dms configuring rbias\n", total_time_ms);

	rc = fg_sec_masked_write(chip, chip->batt_base + ESR_MEAS_EN,
	ESR_MEAS_EN_BIT, ESR_MEAS_EN_BIT);
	if (rc)
	pr_err("Unable to reenable ESR measurements\n");

	/*		/*
	* this may fail, but current time should be still 0,		* this may fail, but current time should be still 0,
	* triggering an immediate update.		* triggering an immediate update.