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Commit 0ffa798d authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branches 'perf/powerpc' and 'perf/bench' into perf/core



Merge reason: Both 'perf bench' and the pending PowerPC changes
              are now ready for the next merge window.

Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
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+1 −1
Original line number Original line Diff line number Diff line
@@ -46,7 +46,7 @@ config DEBUG_STACK_USAGE


config HCALL_STATS
config HCALL_STATS
	bool "Hypervisor call instrumentation"
	bool "Hypervisor call instrumentation"
	depends on PPC_PSERIES && DEBUG_FS
	depends on PPC_PSERIES && DEBUG_FS && TRACEPOINTS
	help
	help
	  Adds code to keep track of the number of hypervisor calls made and
	  Adds code to keep track of the number of hypervisor calls made and
	  the amount of time spent in hypervisor calls.  Wall time spent in
	  the amount of time spent in hypervisor calls.  Wall time spent in
+1 −1
Original line number Original line Diff line number Diff line
@@ -1683,7 +1683,7 @@ CONFIG_HAVE_ARCH_KGDB=y
CONFIG_DEBUG_STACKOVERFLOW=y
CONFIG_DEBUG_STACKOVERFLOW=y
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_HCALL_STATS=y
# CONFIG_HCALL_STATS is not set
# CONFIG_CODE_PATCHING_SELFTEST is not set
# CONFIG_CODE_PATCHING_SELFTEST is not set
# CONFIG_FTR_FIXUP_SELFTEST is not set
# CONFIG_FTR_FIXUP_SELFTEST is not set
# CONFIG_MSI_BITMAP_SELFTEST is not set
# CONFIG_MSI_BITMAP_SELFTEST is not set
+17 −2
Original line number Original line Diff line number Diff line
@@ -19,6 +19,7 @@
#define _ASM_POWERPC_EMULATED_OPS_H
#define _ASM_POWERPC_EMULATED_OPS_H


#include <asm/atomic.h>
#include <asm/atomic.h>
#include <linux/perf_event.h>




#ifdef CONFIG_PPC_EMULATED_STATS
#ifdef CONFIG_PPC_EMULATED_STATS
@@ -57,7 +58,7 @@ extern u32 ppc_warn_emulated;


extern void ppc_warn_emulated_print(const char *type);
extern void ppc_warn_emulated_print(const char *type);


#define PPC_WARN_EMULATED(type)						 \
#define __PPC_WARN_EMULATED(type)					 \
	do {								 \
	do {								 \
		atomic_inc(&ppc_emulated.type.val);			 \
		atomic_inc(&ppc_emulated.type.val);			 \
		if (ppc_warn_emulated)					 \
		if (ppc_warn_emulated)					 \
@@ -66,8 +67,22 @@ extern void ppc_warn_emulated_print(const char *type);


#else /* !CONFIG_PPC_EMULATED_STATS */
#else /* !CONFIG_PPC_EMULATED_STATS */


#define PPC_WARN_EMULATED(type)	do { } while (0)
#define __PPC_WARN_EMULATED(type)	do { } while (0)


#endif /* !CONFIG_PPC_EMULATED_STATS */
#endif /* !CONFIG_PPC_EMULATED_STATS */


#define PPC_WARN_EMULATED(type, regs)					\
	do {								\
		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,		\
			1, 0, regs, 0);					\
		__PPC_WARN_EMULATED(type);				\
	} while (0)

#define PPC_WARN_ALIGNMENT(type, regs)					\
	do {								\
		perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,		\
			1, 0, regs, regs->dar);				\
		__PPC_WARN_EMULATED(type);				\
	} while (0)

#endif /* _ASM_POWERPC_EMULATED_OPS_H */
#endif /* _ASM_POWERPC_EMULATED_OPS_H */
+2 −0
Original line number Original line Diff line number Diff line
@@ -274,6 +274,8 @@ struct hcall_stats {
	unsigned long	num_calls;	/* number of calls (on this CPU) */
	unsigned long	num_calls;	/* number of calls (on this CPU) */
	unsigned long	tb_total;	/* total wall time (mftb) of calls. */
	unsigned long	tb_total;	/* total wall time (mftb) of calls. */
	unsigned long	purr_total;	/* total cpu time (PURR) of calls. */
	unsigned long	purr_total;	/* total cpu time (PURR) of calls. */
	unsigned long	tb_start;
	unsigned long	purr_start;
};
};
#define HCALL_STAT_ARRAY_SIZE	((MAX_HCALL_OPCODE >> 2) + 1)
#define HCALL_STAT_ARRAY_SIZE	((MAX_HCALL_OPCODE >> 2) + 1)


+2 −0
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@@ -489,6 +489,8 @@
#define SPRN_MMCR1	798
#define SPRN_MMCR1	798
#define SPRN_MMCRA	0x312
#define SPRN_MMCRA	0x312
#define   MMCRA_SDSYNC	0x80000000UL /* SDAR synced with SIAR */
#define   MMCRA_SDSYNC	0x80000000UL /* SDAR synced with SIAR */
#define   MMCRA_SDAR_DCACHE_MISS 0x40000000UL
#define   MMCRA_SDAR_ERAT_MISS   0x20000000UL
#define   MMCRA_SIHV	0x10000000UL /* state of MSR HV when SIAR set */
#define   MMCRA_SIHV	0x10000000UL /* state of MSR HV when SIAR set */
#define   MMCRA_SIPR	0x08000000UL /* state of MSR PR when SIAR set */
#define   MMCRA_SIPR	0x08000000UL /* state of MSR PR when SIAR set */
#define   MMCRA_SLOT	0x07000000UL /* SLOT bits (37-39) */
#define   MMCRA_SLOT	0x07000000UL /* SLOT bits (37-39) */
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