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Commit 0f9b9ddf authored by Jeykumar Sankaran's avatar Jeykumar Sankaran
Browse files

clk: qcom: mdss: Add 8992 to 20nm pll supported devices 



Add 8992 to 20nm pll supported devices.

Change-Id: Ic5ca0dc72b83da7a559cfbad1c748b25d1542919
Signed-off-by: default avatarJeykumar Sankaran <jsanka@codeaurora.org>
parent de4cd7bb

Documentation/devicetree/bindings/fb/mdss-pll.txt

+2 −1
Original line number Diff line number Diff line
@@ -9,7 +9,8 @@ Required properties: 
			"qcom,mdss_dsi_pll_8916", "qcom,mdss_dsi_pll_8939",

			"qcom,mdss_dsi_pll_8974", "qcom,mdss_dsi_pll_8994",

			"qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8909",

			"qcom,mdss_hdmi_pll", "qcom,mdss_hdmi_pll_8994"

			"qcom,mdss_hdmi_pll", "qcom,mdss_hdmi_pll_8994",

			"qcom,mdss_dsi_pll_8992", "qcom,mdss_hdmi_pll_8992"

- cell-index:		Specifies the controller used

- reg:			offset and length of the register set for the device.

- reg-names :		names to refer to register sets related to this device

drivers/clk/qcom/mdss/mdss-dsi-pll-20nm.c

+2 −1
Original line number Diff line number Diff line
@@ -603,7 +603,8 @@ int dsi_pll_clock_register_20nm(struct platform_device *pdev, 
		mdss_dsi1_vco_clk_src.priv = pll_res;

	}



	if (pll_res->target_id == MDSS_PLL_TARGET_8994) {

	if ((pll_res->target_id == MDSS_PLL_TARGET_8994) ||

			(pll_res->target_id == MDSS_PLL_TARGET_8992)) {

		if (pll_res->index) {

			rc = of_msm_clock_register(pdev->dev.of_node,

					mdss_dsi_pll_1_cc_8994,

drivers/clk/qcom/mdss/mdss-pll.c

+5 −0
Original line number Diff line number Diff line
@@ -142,6 +142,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev, 
	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8994")) {

		pll_res->pll_interface_type = MDSS_DSI_PLL_20NM;

		pll_res->target_id = MDSS_PLL_TARGET_8994;

	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8992")) {

		pll_res->pll_interface_type = MDSS_DSI_PLL_20NM;

		pll_res->target_id = MDSS_PLL_TARGET_8992;

	} else if (!strcmp(compatible_stream, "qcom,mdss_edp_pll")) {

		pll_res->pll_interface_type = MDSS_EDP_PLL;

	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll")) {
@@ -387,6 +390,8 @@ static const struct of_device_id mdss_pll_dt_match[] = { 
	{.compatible = "qcom,mdss_dsi_pll_8974"},

	{.compatible = "qcom,mdss_dsi_pll_8994"},

	{.compatible = "qcom,mdss_hdmi_pll_8994"},

	{.compatible = "qcom,mdss_dsi_pll_8992"},

	{.compatible = "qcom,mdss_hdmi_pll_8992"},

	{.compatible = "qcom,mdss_dsi_pll_8916"},

	{.compatible = "qcom,mdss_dsi_pll_8939"},

	{.compatible = "qcom,mdss_dsi_pll_8909"},

drivers/clk/qcom/mdss/mdss-pll.h

+1 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ enum { 
enum {

	MDSS_PLL_TARGET_8974,

	MDSS_PLL_TARGET_8994,

	MDSS_PLL_TARGET_8992,

	MDSS_PLL_TARGET_8916,

	MDSS_PLL_TARGET_8939,

	MDSS_PLL_TARGET_8909,

include/dt-bindings/clock/msm-clocks-8992.h

+4 −0
Original line number Diff line number Diff line
@@ -297,6 +297,7 @@ 
#define clk_esc1_clk_src 0x3b0afa42

#define clk_extpclk_clk_src 0xb2c31abd

#define clk_hdmi_clk_src 0xb40aeea9

#define clk_hdmi_20nm_vco_clk 0xacaed5e6

#define clk_vsync_clk_src 0xecb43940

#define clk_rbbmtimer_clk_src 0x17649ecc

#define clk_camss_cci_cci_ahb_clk 0x12aec62d
@@ -383,6 +384,9 @@ 
#define clk_indirect_path_div2_clk_8994 0x21cdcc22

#define clk_ndiv_clk_8994 0x39f41978

#define clk_dsi_vco_clk_8994 0x976ed967

#define clk_mdss_pixel_clk_mux 0xf261a1a6

#define clk_mdss_byte_clk_mux 0x64a23fa0

#define clk_mdss_dsi1_vco_clk_src 0xfcd15658



/* clock_cpu controlled clocks */

#define clk_a57_clk 0x6c7dc3ea