Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0d95580d authored by Anurag Singh's avatar Anurag Singh
Browse files

ARM: dts: msm: add mem_timer and msm_iommu interrupts to bypass list



arch_mem_timer is used on the 8x26 chipset to get around the limitation of
CP15-based timers that are shut down when cores enter standalone power
collapse. However, the corresponding interrupt is not on the MPM bypass
list, as a result of which it is preventing TCXO shutdown in static display
mode (with a smartpanel configuration) even when the CPUs enter
RPM-assisted idle power collapse. This change adds the interrupt to the
bypass list - this is safe to do since when we do idle power collapse, we
rely on the RPM to interrupt the cores.

The msm_iommu_interrupts (msm_iommu_global_cfg_irq and
msm_iommu_global_client_irq) are needed for debugging SMMU configuration
errors and so can be bypassed as well.

Change-Id: I6e802c99a9530490555db56a65b622ff33037fb4
Signed-off-by: default avatarAnurag Singh <anursing@codeaurora.org>
parent af289785
Loading
Loading
Loading
Loading
+3 −0
Original line number Diff line number Diff line
@@ -184,6 +184,7 @@
			<0xff 18>,  /* APC_qgicQTmrSecPhysIrptReq */
			<0xff 19>,  /* APC_qgicQTmrNonSecPhysIrptReq */
			<0xff 35>,  /* WDT_barkInt */
			<0xff 39>,  /* arch_mem_timer */
			<0xff 40>,  /* qtmr_phy_irq[0] */
			<0xff 47>,  /* rbif_irq[0] */
			<0xff 56>,  /* q6_wdog_expired_irq */
@@ -241,6 +242,8 @@
			<0xff 253>, /* sdc2_pwr_cmd_irq */
			<0xff 258>, /* rpm_ipc(28) */
			<0xff 259>, /* rpm_ipc(29) */
			<0xff 261>, /* msm_iommu_global_cfg_irq */
			<0xff 263>, /* msm_iommu_global_client_irq */
			<0xff 269>, /* rpm_wdog_expired_irq */
			<0xff 270>, /* blsp1_bam_irq[0] */
			<0xff 275>, /* rpm_ipc(30) */
+3 −0
Original line number Diff line number Diff line
@@ -196,6 +196,7 @@
			<0xff 18>,  /* APC_qgicQTmrSecPhysIrptReq */
			<0xff 19>,  /* APC_qgicQTmrNonSecPhysIrptReq */
			<0xff 35>,  /* WDT_barkInt */
			<0xff 39>,  /* arch_mem_timer */
			<0xff 40>,  /* qtmr_phy_irq[0] */
			<0xff 47>,  /* rbif_irq[0] */
			<0xff 56>,  /* q6_wdog_expired_irq */
@@ -253,6 +254,8 @@
			<0xff 253>, /* sdc2_pwr_cmd_irq */
			<0xff 258>, /* rpm_ipc(28) */
			<0xff 259>, /* rpm_ipc(29) */
			<0xff 261>, /* msm_iommu_global_cfg_irq */
			<0xff 263>, /* msm_iommu_global_client_irq */
			<0xff 269>, /* rpm_wdog_expired_irq */
			<0xff 270>, /* blsp1_bam_irq[0] */
			<0xff 275>, /* rpm_ipc(30) */