Merge "clock-plutonium: Rename SVS2 to LOWER" (0d6744bd) · Commits · e / devices / android_kernel_sony_msm8994

drivers/clk/qcom/clock-gcc-plutonium.c

+55 −55

Original line number	Diff line number	Diff line
		@@ -278,7 +278,7 @@ static struct pll_vote_clk gpll4 = {
		.parent = &gcc_xo.c,
		.dbg_name = "gpll4",
		.ops = &clk_ops_pll_vote,
		VDD_DIG_FMAX_MAP3(SVS2, 400000000, LOW, 800000000,
		VDD_DIG_FMAX_MAP3(LOWER, 400000000, LOW, 800000000,
		NOMINAL, 1600000000),
		CLK_INIT(gpll4.c),
		},
		@@ -301,7 +301,7 @@ static struct rcg_clk ufs_axi_clk_src = {
		.c = {
		.dbg_name = "ufs_axi_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP4(SVS2, 50000000, LOW, 100000000,
		VDD_DIG_FMAX_MAP4(LOWER, 50000000, LOW, 100000000,
		NOMINAL, 200000000, HIGH, 240000000),
		CLK_INIT(ufs_axi_clk_src.c),
		},
		@@ -321,7 +321,7 @@ static struct rcg_clk usb30_master_clk_src = {
		.c = {
		.dbg_name = "usb30_master_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP2(SVS2, 62500000, LOW, 125000000),
		VDD_DIG_FMAX_MAP2(LOWER, 62500000, LOW, 125000000),
		CLK_INIT(usb30_master_clk_src.c),
		},
		};
		@@ -341,7 +341,7 @@ static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_qup1_i2c_apps_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 19200000, LOW, 50000000),
		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
		CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
		},
		};
		@@ -366,7 +366,7 @@ static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_qup1_spi_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 12500000, LOW, 25000000,
		VDD_DIG_FMAX_MAP3(LOWER, 12500000, LOW, 25000000,
		NOMINAL, 50000000),
		CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
		},
		@@ -381,7 +381,7 @@ static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_qup2_i2c_apps_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 19200000, LOW, 50000000),
		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
		CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
		},
		};
		@@ -395,7 +395,7 @@ static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_qup2_spi_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 12500000, LOW, 25000000,
		VDD_DIG_FMAX_MAP3(LOWER, 12500000, LOW, 25000000,
		NOMINAL, 50000000),
		CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
		},
		@@ -410,7 +410,7 @@ static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_qup3_i2c_apps_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 19200000, LOW, 50000000),
		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
		CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
		},
		};
		@@ -424,7 +424,7 @@ static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_qup3_spi_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 12500000, LOW, 25000000,
		VDD_DIG_FMAX_MAP3(LOWER, 12500000, LOW, 25000000,
		NOMINAL, 50000000),
		CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
		},
		@@ -439,7 +439,7 @@ static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_qup4_i2c_apps_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 19200000, LOW, 50000000),
		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
		CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
		},
		};
		@@ -453,7 +453,7 @@ static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_qup4_spi_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 12500000, LOW, 25000000,
		VDD_DIG_FMAX_MAP3(LOWER, 12500000, LOW, 25000000,
		NOMINAL, 50000000),
		CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
		},
		@@ -468,7 +468,7 @@ static struct rcg_clk blsp1_qup5_i2c_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_qup5_i2c_apps_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 19200000, LOW, 50000000),
		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
		CLK_INIT(blsp1_qup5_i2c_apps_clk_src.c),
		},
		};
		@@ -482,7 +482,7 @@ static struct rcg_clk blsp1_qup5_spi_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_qup5_spi_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 12500000, LOW, 25000000,
		VDD_DIG_FMAX_MAP3(LOWER, 12500000, LOW, 25000000,
		NOMINAL, 50000000),
		CLK_INIT(blsp1_qup5_spi_apps_clk_src.c),
		},
		@@ -497,7 +497,7 @@ static struct rcg_clk blsp1_qup6_i2c_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_qup6_i2c_apps_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 19200000, LOW, 50000000),
		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
		CLK_INIT(blsp1_qup6_i2c_apps_clk_src.c),
		},
		};
		@@ -511,7 +511,7 @@ static struct rcg_clk blsp1_qup6_spi_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_qup6_spi_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 12500000, LOW, 25000000,
		VDD_DIG_FMAX_MAP3(LOWER, 12500000, LOW, 25000000,
		NOMINAL, 50000000),
		CLK_INIT(blsp1_qup6_spi_apps_clk_src.c),
		},
		@@ -545,7 +545,7 @@ static struct rcg_clk blsp1_uart1_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_uart1_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 15790000, LOW, 31580000,
		VDD_DIG_FMAX_MAP3(LOWER, 15790000, LOW, 31580000,
		NOMINAL, 63160000),
		CLK_INIT(blsp1_uart1_apps_clk_src.c),
		},
		@@ -560,7 +560,7 @@ static struct rcg_clk blsp1_uart2_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_uart2_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 15790000, LOW, 31580000,
		VDD_DIG_FMAX_MAP3(LOWER, 15790000, LOW, 31580000,
		NOMINAL, 63160000),
		CLK_INIT(blsp1_uart2_apps_clk_src.c),
		},
		@@ -575,7 +575,7 @@ static struct rcg_clk blsp1_uart3_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_uart3_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 15790000, LOW, 31580000,
		VDD_DIG_FMAX_MAP3(LOWER, 15790000, LOW, 31580000,
		NOMINAL, 63160000),
		CLK_INIT(blsp1_uart3_apps_clk_src.c),
		},
		@@ -590,7 +590,7 @@ static struct rcg_clk blsp1_uart4_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_uart4_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 15790000, LOW, 31580000,
		VDD_DIG_FMAX_MAP3(LOWER, 15790000, LOW, 31580000,
		NOMINAL, 63160000),
		CLK_INIT(blsp1_uart4_apps_clk_src.c),
		},
		@@ -605,7 +605,7 @@ static struct rcg_clk blsp1_uart5_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_uart5_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 15790000, LOW, 31580000,
		VDD_DIG_FMAX_MAP3(LOWER, 15790000, LOW, 31580000,
		NOMINAL, 63160000),
		CLK_INIT(blsp1_uart5_apps_clk_src.c),
		},
		@@ -620,7 +620,7 @@ static struct rcg_clk blsp1_uart6_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_uart6_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 15790000, LOW, 31580000,
		VDD_DIG_FMAX_MAP3(LOWER, 15790000, LOW, 31580000,
		NOMINAL, 63160000),
		CLK_INIT(blsp1_uart6_apps_clk_src.c),
		},
		@@ -635,7 +635,7 @@ static struct rcg_clk blsp2_qup1_i2c_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_qup1_i2c_apps_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 19200000, LOW, 50000000),
		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
		CLK_INIT(blsp2_qup1_i2c_apps_clk_src.c),
		},
		};
		@@ -649,7 +649,7 @@ static struct rcg_clk blsp2_qup1_spi_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_qup1_spi_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 12500000, LOW, 25000000,
		VDD_DIG_FMAX_MAP3(LOWER, 12500000, LOW, 25000000,
		NOMINAL, 50000000),
		CLK_INIT(blsp2_qup1_spi_apps_clk_src.c),
		},
		@@ -664,7 +664,7 @@ static struct rcg_clk blsp2_qup2_i2c_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_qup2_i2c_apps_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 19200000, LOW, 50000000),
		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
		CLK_INIT(blsp2_qup2_i2c_apps_clk_src.c),
		},
		};
		@@ -678,7 +678,7 @@ static struct rcg_clk blsp2_qup2_spi_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_qup2_spi_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 12500000, LOW, 25000000,
		VDD_DIG_FMAX_MAP3(LOWER, 12500000, LOW, 25000000,
		NOMINAL, 50000000),
		CLK_INIT(blsp2_qup2_spi_apps_clk_src.c),
		},
		@@ -693,7 +693,7 @@ static struct rcg_clk blsp2_qup3_i2c_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_qup3_i2c_apps_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 19200000, LOW, 50000000),
		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
		CLK_INIT(blsp2_qup3_i2c_apps_clk_src.c),
		},
		};
		@@ -707,7 +707,7 @@ static struct rcg_clk blsp2_qup3_spi_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_qup3_spi_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 12500000, LOW, 25000000,
		VDD_DIG_FMAX_MAP3(LOWER, 12500000, LOW, 25000000,
		NOMINAL, 50000000),
		CLK_INIT(blsp2_qup3_spi_apps_clk_src.c),
		},
		@@ -722,7 +722,7 @@ static struct rcg_clk blsp2_qup4_i2c_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_qup4_i2c_apps_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 19200000, LOW, 50000000),
		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
		CLK_INIT(blsp2_qup4_i2c_apps_clk_src.c),
		},
		};
		@@ -736,7 +736,7 @@ static struct rcg_clk blsp2_qup4_spi_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_qup4_spi_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 12500000, LOW, 25000000,
		VDD_DIG_FMAX_MAP3(LOWER, 12500000, LOW, 25000000,
		NOMINAL, 50000000),
		CLK_INIT(blsp2_qup4_spi_apps_clk_src.c),
		},
		@@ -751,7 +751,7 @@ static struct rcg_clk blsp2_qup5_i2c_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_qup5_i2c_apps_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 19200000, LOW, 50000000),
		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
		CLK_INIT(blsp2_qup5_i2c_apps_clk_src.c),
		},
		};
		@@ -765,7 +765,7 @@ static struct rcg_clk blsp2_qup5_spi_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_qup5_spi_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 12500000, LOW, 25000000,
		VDD_DIG_FMAX_MAP3(LOWER, 12500000, LOW, 25000000,
		NOMINAL, 50000000),
		CLK_INIT(blsp2_qup5_spi_apps_clk_src.c),
		},
		@@ -780,7 +780,7 @@ static struct rcg_clk blsp2_qup6_i2c_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_qup6_i2c_apps_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 19200000, LOW, 50000000),
		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
		CLK_INIT(blsp2_qup6_i2c_apps_clk_src.c),
		},
		};
		@@ -794,7 +794,7 @@ static struct rcg_clk blsp2_qup6_spi_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_qup6_spi_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 12500000, LOW, 25000000,
		VDD_DIG_FMAX_MAP3(LOWER, 12500000, LOW, 25000000,
		NOMINAL, 50000000),
		CLK_INIT(blsp2_qup6_spi_apps_clk_src.c),
		},
		@@ -809,7 +809,7 @@ static struct rcg_clk blsp2_uart1_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_uart1_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 15790000, LOW, 31580000,
		VDD_DIG_FMAX_MAP3(LOWER, 15790000, LOW, 31580000,
		NOMINAL, 63160000),
		CLK_INIT(blsp2_uart1_apps_clk_src.c),
		},
		@@ -824,7 +824,7 @@ static struct rcg_clk blsp2_uart2_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_uart2_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 15790000, LOW, 31580000,
		VDD_DIG_FMAX_MAP3(LOWER, 15790000, LOW, 31580000,
		NOMINAL, 63160000),
		CLK_INIT(blsp2_uart2_apps_clk_src.c),
		},
		@@ -839,7 +839,7 @@ static struct rcg_clk blsp2_uart3_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_uart3_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 15790000, LOW, 31580000,
		VDD_DIG_FMAX_MAP3(LOWER, 15790000, LOW, 31580000,
		NOMINAL, 63160000),
		CLK_INIT(blsp2_uart3_apps_clk_src.c),
		},
		@@ -854,7 +854,7 @@ static struct rcg_clk blsp2_uart4_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_uart4_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 15790000, LOW, 31580000,
		VDD_DIG_FMAX_MAP3(LOWER, 15790000, LOW, 31580000,
		NOMINAL, 63160000),
		CLK_INIT(blsp2_uart4_apps_clk_src.c),
		},
		@@ -869,7 +869,7 @@ static struct rcg_clk blsp2_uart5_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_uart5_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 15790000, LOW, 31580000,
		VDD_DIG_FMAX_MAP3(LOWER, 15790000, LOW, 31580000,
		NOMINAL, 63160000),
		CLK_INIT(blsp2_uart5_apps_clk_src.c),
		},
		@@ -884,7 +884,7 @@ static struct rcg_clk blsp2_uart6_apps_clk_src = {
		.c = {
		.dbg_name = "blsp2_uart6_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 15790000, LOW, 31580000,
		VDD_DIG_FMAX_MAP3(LOWER, 15790000, LOW, 31580000,
		NOMINAL, 63160000),
		CLK_INIT(blsp2_uart6_apps_clk_src.c),
		},
		@@ -906,7 +906,7 @@ static struct rcg_clk gp1_clk_src = {
		.c = {
		.dbg_name = "gp1_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 50000000, LOW, 100000000,
		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
		NOMINAL, 200000000),
		CLK_INIT(gp1_clk_src.c),
		},
		@@ -928,7 +928,7 @@ static struct rcg_clk gp2_clk_src = {
		.c = {
		.dbg_name = "gp2_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 50000000, LOW, 100000000,
		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
		NOMINAL, 200000000),
		CLK_INIT(gp2_clk_src.c),
		},
		@@ -950,7 +950,7 @@ static struct rcg_clk gp3_clk_src = {
		.c = {
		.dbg_name = "gp3_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 50000000, LOW, 100000000,
		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
		NOMINAL, 200000000),
		CLK_INIT(gp3_clk_src.c),
		},
		@@ -970,7 +970,7 @@ static struct rcg_clk pcie_0_aux_clk_src = {
		.c = {
		.dbg_name = "pcie_0_aux_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP1(SVS2, 1011000),
		VDD_DIG_FMAX_MAP1(LOWER, 1011000),
		CLK_INIT(pcie_0_aux_clk_src.c),
		},
		};
		@@ -989,7 +989,7 @@ static struct rcg_clk pcie_0_pipe_clk_src = {
		.c = {
		.dbg_name = "pcie_0_pipe_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 62500000, LOW, 125000000),
		VDD_DIG_FMAX_MAP2(LOWER, 62500000, LOW, 125000000),
		CLK_INIT(pcie_0_pipe_clk_src.c),
		},
		};
		@@ -1008,7 +1008,7 @@ static struct rcg_clk pcie_1_aux_clk_src = {
		.c = {
		.dbg_name = "pcie_1_aux_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP1(SVS2, 1011000),
		VDD_DIG_FMAX_MAP1(LOWER, 1011000),
		CLK_INIT(pcie_1_aux_clk_src.c),
		},
		};
		@@ -1022,7 +1022,7 @@ static struct rcg_clk pcie_1_pipe_clk_src = {
		.c = {
		.dbg_name = "pcie_1_pipe_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 62500000, LOW, 125000000),
		VDD_DIG_FMAX_MAP2(LOWER, 62500000, LOW, 125000000),
		CLK_INIT(pcie_1_pipe_clk_src.c),
		},
		};
		@@ -1041,7 +1041,7 @@ static struct rcg_clk pdm2_clk_src = {
		.c = {
		.dbg_name = "pdm2_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 19200000, LOW, 60000000),
		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 60000000),
		CLK_INIT(pdm2_clk_src.c),
		},
		};
		@@ -1067,7 +1067,7 @@ static struct rcg_clk sdcc1_apps_clk_src = {
		.c = {
		.dbg_name = "sdcc1_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 100000000, LOW, 200000000,
		VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 200000000,
		NOMINAL, 400000000),
		CLK_INIT(sdcc1_apps_clk_src.c),
		},
		@@ -1093,7 +1093,7 @@ static struct rcg_clk sdcc2_apps_clk_src = {
		.c = {
		.dbg_name = "sdcc2_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 50000000, LOW, 100000000,
		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
		NOMINAL, 200000000),
		CLK_INIT(sdcc2_apps_clk_src.c),
		},
		@@ -1108,7 +1108,7 @@ static struct rcg_clk sdcc3_apps_clk_src = {
		.c = {
		.dbg_name = "sdcc3_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 50000000, LOW, 100000000,
		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
		NOMINAL, 200000000),
		CLK_INIT(sdcc3_apps_clk_src.c),
		},
		@@ -1123,7 +1123,7 @@ static struct rcg_clk sdcc4_apps_clk_src = {
		.c = {
		.dbg_name = "sdcc4_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 19200000, LOW, 50000000,
		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 50000000,
		NOMINAL, 100000000),
		CLK_INIT(sdcc4_apps_clk_src.c),
		},
		@@ -1143,7 +1143,7 @@ static struct rcg_clk tsif_ref_clk_src = {
		.c = {
		.dbg_name = "tsif_ref_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP1(SVS2, 105500),
		VDD_DIG_FMAX_MAP1(LOWER, 105500),
		CLK_INIT(tsif_ref_clk_src.c),
		},
		};
		@@ -1166,7 +1166,7 @@ static struct rcg_clk usb30_mock_utmi_clk_src = {
		.c = {
		.dbg_name = "usb30_mock_utmi_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP2(SVS2, 40000000, LOW, 60000000),
		VDD_DIG_FMAX_MAP2(LOWER, 40000000, LOW, 60000000),
		CLK_INIT(usb30_mock_utmi_clk_src.c),
		},
		};
		@@ -1185,7 +1185,7 @@ static struct rcg_clk usb3_phy_aux_clk_src = {
		.c = {
		.dbg_name = "usb3_phy_aux_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP1(SVS2, 1200000),
		VDD_DIG_FMAX_MAP1(LOWER, 1200000),
		CLK_INIT(usb3_phy_aux_clk_src.c),
		},
		};
		@@ -1204,7 +1204,7 @@ static struct rcg_clk usb_hs_system_clk_src = {
		.c = {
		.dbg_name = "usb_hs_system_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP3(SVS2, 19200000, LOW, 60000000,
		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 60000000,
		NOMINAL, 75000000),
		CLK_INIT(usb_hs_system_clk_src.c),
		},

drivers/clk/qcom/clock-mmss-plutonium.c

+35 −35

Original line number	Diff line number	Diff line
		@@ -217,7 +217,7 @@ static struct pll_vote_clk mmpll0 = {
		.parent = &mmsscc_xo.c,
		.dbg_name = "mmpll0",
		.ops = &clk_ops_pll_vote,
		VDD_DIG_FMAX_MAP2(SVS2, 400000000, NOMINAL, 800000000),
		VDD_DIG_FMAX_MAP2(LOWER, 400000000, NOMINAL, 800000000),
		CLK_INIT(mmpll0.c),
		},
		};
		@@ -234,7 +234,7 @@ static struct alpha_pll_clk mmpll4 = {
		.rate = 930000000,
		.dbg_name = "mmpll4",
		.ops = &clk_ops_fixed_alpha_pll,
		VDD_DIG_FMAX_MAP2(SVS2, 650000000, NOMINAL, 1300000000),
		VDD_DIG_FMAX_MAP2(LOWER, 650000000, NOMINAL, 1300000000),
		CLK_INIT(mmpll4.c),
		},
		};
		@@ -251,7 +251,7 @@ static struct pll_vote_clk mmpll1 = {
		.parent = &mmsscc_xo.c,
		.dbg_name = "mmpll1",
		.ops = &clk_ops_pll_vote,
		VDD_DIG_FMAX_MAP2(SVS2, 650000000, NOMINAL, 1300000000),
		VDD_DIG_FMAX_MAP2(LOWER, 650000000, NOMINAL, 1300000000),
		CLK_INIT(mmpll1.c),
		},
		};
		@@ -268,7 +268,7 @@ static struct alpha_pll_clk mmpll3 = {
		.rate = 930000000,
		.dbg_name = "mmpll3",
		.ops = &clk_ops_fixed_alpha_pll,
		VDD_DIG_FMAX_MAP2(SVS2, 650000000, NOMINAL, 1300000000),
		VDD_DIG_FMAX_MAP2(LOWER, 650000000, NOMINAL, 1300000000),
		CLK_INIT(mmpll3.c),
		},
		};
		@@ -293,7 +293,7 @@ static struct rcg_clk axi_clk_src = {
		.c = {
		.dbg_name = "axi_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP4(SVS2, 75000000, LOW, 150000000,
		VDD_DIG_FMAX_MAP4(LOWER, 75000000, LOW, 150000000,
		NOMINAL, 333430000, HIGH, 466800000),
		CLK_INIT(axi_clk_src.c),
		},
		@@ -310,7 +310,7 @@ static struct alpha_pll_clk mmpll5 = {
		.rate = 960000000,
		.dbg_name = "mmpll5",
		.ops = &clk_ops_fixed_alpha_pll,
		VDD_DIG_FMAX_MAP2(SVS2, 650000000, NOMINAL, 1300000000),
		VDD_DIG_FMAX_MAP2(LOWER, 650000000, NOMINAL, 1300000000),
		CLK_INIT(mmpll5.c),
		},
		};
		@@ -331,7 +331,7 @@ static struct rcg_clk csi0_clk_src = {
		.c = {
		.dbg_name = "csi0_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP3(SVS2, 50000000, LOW, 100000000,
		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
		NOMINAL, 266670000),
		CLK_INIT(csi0_clk_src.c),
		},
		@@ -356,7 +356,7 @@ static struct rcg_clk vcodec0_clk_src = {
		.c = {
		.dbg_name = "vcodec0_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP4(SVS2, 66670000, LOW, 133330000,
		VDD_DIG_FMAX_MAP4(LOWER, 66670000, LOW, 133330000,
		NOMINAL, 266670000, HIGH, 510000000),
		CLK_INIT(vcodec0_clk_src.c),
		},
		@@ -377,7 +377,7 @@ static struct rcg_clk csi1_clk_src = {
		.c = {
		.dbg_name = "csi1_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP3(SVS2, 50000000, LOW, 100000000,
		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
		NOMINAL, 266670000),
		CLK_INIT(csi1_clk_src.c),
		},
		@@ -398,7 +398,7 @@ static struct rcg_clk csi2_clk_src = {
		.c = {
		.dbg_name = "csi2_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP3(SVS2, 50000000, LOW, 100000000,
		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
		NOMINAL, 266670000),
		CLK_INIT(csi2_clk_src.c),
		},
		@@ -419,7 +419,7 @@ static struct rcg_clk csi3_clk_src = {
		.c = {
		.dbg_name = "csi3_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP3(SVS2, 50000000, LOW, 100000000,
		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
		NOMINAL, 266670000),
		CLK_INIT(csi3_clk_src.c),
		},
		@@ -444,7 +444,7 @@ static struct rcg_clk vfe0_clk_src = {
		.c = {
		.dbg_name = "vfe0_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP4(SVS2, 100000000, LOW, 200000000,
		VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 200000000,
		NOMINAL, 465000000, HIGH, 600000000),
		CLK_INIT(vfe0_clk_src.c),
		},
		@@ -469,7 +469,7 @@ static struct rcg_clk vfe1_clk_src = {
		.c = {
		.dbg_name = "vfe1_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP4(SVS2, 100000000, LOW, 200000000,
		VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 200000000,
		NOMINAL, 465000000, HIGH, 600000000),
		CLK_INIT(vfe1_clk_src.c),
		},
		@@ -493,7 +493,7 @@ static struct rcg_clk cpp_clk_src = {
		.c = {
		.dbg_name = "cpp_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP4(SVS2, 100000000, LOW, 200000000,
		VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 200000000,
		NOMINAL, 465000000, HIGH, 620000000),
		CLK_INIT(cpp_clk_src.c),
		},
		@@ -518,7 +518,7 @@ static struct rcg_clk jpeg1_clk_src = {
		.c = {
		.dbg_name = "jpeg1_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP4(SVS2, 75000000, LOW, 150000000,
		VDD_DIG_FMAX_MAP4(LOWER, 75000000, LOW, 150000000,
		NOMINAL, 320000000, HIGH, 465000000),
		CLK_INIT(jpeg1_clk_src.c),
		},
		@@ -542,7 +542,7 @@ static struct rcg_clk jpeg2_clk_src = {
		.c = {
		.dbg_name = "jpeg2_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP4(SVS2, 75000000, LOW, 133330000,
		VDD_DIG_FMAX_MAP4(LOWER, 75000000, LOW, 133330000,
		NOMINAL, 266670000, HIGH, 320000000),
		CLK_INIT(jpeg2_clk_src.c),
		},
		@@ -564,7 +564,7 @@ static struct rcg_clk csi2phytimer_clk_src = {
		.c = {
		.dbg_name = "csi2phytimer_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP3(SVS2, 50000000, LOW, 100000000,
		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
		NOMINAL, 200000000),
		CLK_INIT(csi2phytimer_clk_src.c),
		},
		@@ -586,7 +586,7 @@ static struct rcg_clk fd_core_clk_src = {
		.c = {
		.dbg_name = "fd_core_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP3(SVS2, 60000000, LOW, 200000000,
		VDD_DIG_FMAX_MAP3(LOWER, 60000000, LOW, 200000000,
		NOMINAL, 400000000),
		CLK_INIT(fd_core_clk_src.c),
		},
		@@ -610,7 +610,7 @@ static struct rcg_clk mdp_clk_src = {
		.c = {
		.dbg_name = "mdp_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP4(SVS2, 85710000, LOW, 171430000,
		VDD_DIG_FMAX_MAP4(LOWER, 85710000, LOW, 171430000,
		NOMINAL, 320000000, HIGH, 400000000),
		CLK_INIT(mdp_clk_src.c),
		},
		@@ -635,7 +635,7 @@ static struct rcg_clk ocmemnoc_clk_src = {
		.c = {
		.dbg_name = "ocmemnoc_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP4(SVS2, 75000000, LOW, 150000000,
		VDD_DIG_FMAX_MAP4(LOWER, 75000000, LOW, 150000000,
		NOMINAL, 320000000, HIGH, 400000000),
		CLK_INIT(ocmemnoc_clk_src.c),
		},
		@@ -656,7 +656,7 @@ static struct rcg_clk cci_clk_src = {
		.c = {
		.dbg_name = "cci_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 19200000, LOW, 50000000,
		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 50000000,
		NOMINAL, 100000000),
		CLK_INIT(cci_clk_src.c),
		},
		@@ -681,7 +681,7 @@ static struct rcg_clk mmss_gp0_clk_src = {
		.c = {
		.dbg_name = "mmss_gp0_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 50000000, LOW, 100000000,
		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
		NOMINAL, 200000000),
		CLK_INIT(mmss_gp0_clk_src.c),
		},
		@@ -706,7 +706,7 @@ static struct rcg_clk mmss_gp1_clk_src = {
		.c = {
		.dbg_name = "mmss_gp1_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP3(SVS2, 50000000, LOW, 100000000,
		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
		NOMINAL, 200000000),
		CLK_INIT(mmss_gp1_clk_src.c),
		},
		@@ -731,7 +731,7 @@ static struct rcg_clk jpeg0_clk_src = {
		.c = {
		.dbg_name = "jpeg0_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP4(SVS2, 75000000, LOW, 150000000,
		VDD_DIG_FMAX_MAP4(LOWER, 75000000, LOW, 150000000,
		NOMINAL, 320000000, HIGH, 465000000),
		CLK_INIT(jpeg0_clk_src.c),
		},
		@@ -756,7 +756,7 @@ static struct rcg_clk jpeg_dma_clk_src = {
		.c = {
		.dbg_name = "jpeg_dma_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP4(SVS2, 75000000, LOW, 150000000,
		VDD_DIG_FMAX_MAP4(LOWER, 75000000, LOW, 150000000,
		NOMINAL, 320000000, HIGH, 465000000),
		CLK_INIT(jpeg_dma_clk_src.c),
		},
		@@ -785,7 +785,7 @@ static struct rcg_clk mclk0_clk_src = {
		.c = {
		.dbg_name = "mclk0_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP2(SVS2, 33330000, LOW, 66670000),
		VDD_DIG_FMAX_MAP2(LOWER, 33330000, LOW, 66670000),
		CLK_INIT(mclk0_clk_src.c),
		},
		};
		@@ -813,7 +813,7 @@ static struct rcg_clk mclk1_clk_src = {
		.c = {
		.dbg_name = "mclk1_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP2(SVS2, 33330000, LOW, 66670000),
		VDD_DIG_FMAX_MAP2(LOWER, 33330000, LOW, 66670000),
		CLK_INIT(mclk1_clk_src.c),
		},
		};
		@@ -841,7 +841,7 @@ static struct rcg_clk mclk2_clk_src = {
		.c = {
		.dbg_name = "mclk2_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP2(SVS2, 33330000, LOW, 66670000),
		VDD_DIG_FMAX_MAP2(LOWER, 33330000, LOW, 66670000),
		CLK_INIT(mclk2_clk_src.c),
		},
		};
		@@ -869,7 +869,7 @@ static struct rcg_clk mclk3_clk_src = {
		.c = {
		.dbg_name = "mclk3_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP2(SVS2, 33330000, LOW, 66670000),
		VDD_DIG_FMAX_MAP2(LOWER, 33330000, LOW, 66670000),
		CLK_INIT(mclk3_clk_src.c),
		},
		};
		@@ -890,7 +890,7 @@ static struct rcg_clk csi0phytimer_clk_src = {
		.c = {
		.dbg_name = "csi0phytimer_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP3(SVS2, 50000000, LOW, 100000000,
		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
		NOMINAL, 200000000),
		CLK_INIT(csi0phytimer_clk_src.c),
		},
		@@ -912,7 +912,7 @@ static struct rcg_clk csi1phytimer_clk_src = {
		.c = {
		.dbg_name = "csi1phytimer_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP3(SVS2, 50000000, LOW, 100000000,
		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
		NOMINAL, 200000000),
		CLK_INIT(csi1phytimer_clk_src.c),
		},
		@@ -932,7 +932,7 @@ static struct rcg_clk esc0_clk_src = {
		.c = {
		.dbg_name = "esc0_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP1(SVS2, 19200000),
		VDD_DIG_FMAX_MAP1(LOWER, 19200000),
		CLK_INIT(esc0_clk_src.c),
		},
		};
		@@ -951,7 +951,7 @@ static struct rcg_clk esc1_clk_src = {
		.c = {
		.dbg_name = "esc1_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP1(SVS2, 19200000),
		VDD_DIG_FMAX_MAP1(LOWER, 19200000),
		CLK_INIT(esc1_clk_src.c),
		},
		};
		@@ -970,7 +970,7 @@ static struct rcg_clk hdmi_clk_src = {
		.c = {
		.dbg_name = "hdmi_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP1(SVS2, 19200000),
		VDD_DIG_FMAX_MAP1(LOWER, 19200000),
		CLK_INIT(hdmi_clk_src.c),
		},
		};
		@@ -989,7 +989,7 @@ static struct rcg_clk vsync_clk_src = {
		.c = {
		.dbg_name = "vsync_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP1(SVS2, 19200000),
		VDD_DIG_FMAX_MAP1(LOWER, 19200000),
		CLK_INIT(vsync_clk_src.c),
		},
		};

drivers/clk/qcom/vdd-level-plutonium.h

+2 −3

Original line number	Diff line number	Diff line
		@@ -51,18 +51,17 @@

		enum vdd_dig_levels {
		VDD_DIG_NONE,
		VDD_DIG_SVS2, /* SVS2 */
		VDD_DIG_LOWER, /* SVS2 */
		VDD_DIG_LOW, /* SVS */
		VDD_DIG_NOMINAL, /* NOMINAL */
		VDD_DIG_HIGH, /* Turbo */
		VDD_DIG_NUM
		};

		/* TODO: Put in real SVS2 corner */
		static int vdd_corner[] = {
		RPM_REGULATOR_CORNER_NONE, /* VDD_DIG_NONE */
		RPM_REGULATOR_CORNER_SVS_SOC, /* SVS2 is remapped to SVS */
		RPM_REGULATOR_CORNER_SVS_SOC, /* VDD_DIG_SVS */
		RPM_REGULATOR_CORNER_SVS_SOC, /* SVS2 place holder */
		RPM_REGULATOR_CORNER_NORMAL, /* VDD_DIG_NOMINAL */
		RPM_REGULATOR_CORNER_SUPER_TURBO, /* VDD_DIG_TURBO */
		};