Loading arch/arm64/include/asm/smp_plat.h +2 −0 Original line number Diff line number Diff line Loading @@ -34,10 +34,12 @@ static inline u32 mpidr_hash_size(void) return 1 << mpidr_hash.bits; } extern void secondary_holding_pen(void); /* * Logical CPU mapping. */ extern u64 __cpu_logical_map[NR_CPUS]; #define cpu_logical_map(cpu) __cpu_logical_map[cpu] extern volatile unsigned long secondary_holding_pen_release; #endif /* __ASM_SMP_PLAT_H */ arch/arm64/kernel/smp.c +1 −0 Original line number Diff line number Diff line Loading @@ -55,6 +55,7 @@ * where to place its SVC stack */ struct secondary_data secondary_data; volatile unsigned long secondary_holding_pen_release = INVALID_HWID; enum ipi_msg_type { IPI_RESCHEDULE, Loading arch/arm64/kernel/smp_spin_table.c +0 −3 Original line number Diff line number Diff line Loading @@ -26,9 +26,6 @@ #include <asm/cputype.h> #include <asm/smp_plat.h> extern void secondary_holding_pen(void); volatile unsigned long secondary_holding_pen_release = INVALID_HWID; static phys_addr_t cpu_release_addr[NR_CPUS]; static DEFINE_RAW_SPINLOCK(boot_lock); Loading Loading
arch/arm64/include/asm/smp_plat.h +2 −0 Original line number Diff line number Diff line Loading @@ -34,10 +34,12 @@ static inline u32 mpidr_hash_size(void) return 1 << mpidr_hash.bits; } extern void secondary_holding_pen(void); /* * Logical CPU mapping. */ extern u64 __cpu_logical_map[NR_CPUS]; #define cpu_logical_map(cpu) __cpu_logical_map[cpu] extern volatile unsigned long secondary_holding_pen_release; #endif /* __ASM_SMP_PLAT_H */
arch/arm64/kernel/smp.c +1 −0 Original line number Diff line number Diff line Loading @@ -55,6 +55,7 @@ * where to place its SVC stack */ struct secondary_data secondary_data; volatile unsigned long secondary_holding_pen_release = INVALID_HWID; enum ipi_msg_type { IPI_RESCHEDULE, Loading
arch/arm64/kernel/smp_spin_table.c +0 −3 Original line number Diff line number Diff line Loading @@ -26,9 +26,6 @@ #include <asm/cputype.h> #include <asm/smp_plat.h> extern void secondary_holding_pen(void); volatile unsigned long secondary_holding_pen_release = INVALID_HWID; static phys_addr_t cpu_release_addr[NR_CPUS]; static DEFINE_RAW_SPINLOCK(boot_lock); Loading