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Commit 0d05cd05 authored by Vasko Kalanoski's avatar Vasko Kalanoski
Browse files

ARM: dts: msm: set correct order of 8994 csiphy clocks 



set correct order of 8994 csiphy clocks to fix warning
which tell that clock is enabled before being set the rate

Change-Id: If16c619ccdc0a952d16cdcb959668c189e217877
Signed-off-by: default avatarVasko Kalanoski <vaskok@codeaurora.org>
parent f3406196

arch/arm/boot/dts/qcom/msm8994-camera.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -96,9 +96,9 @@ 
		qcom,gdscr-vdd-supply = <&gdsc_camss_top>;

		clocks = <&clock_mmss clk_camss_top_ahb_clk>,

			<&clock_mmss clk_camss_ispif_ahb_clk>,

			<&clock_mmss clk_csi0_clk_src>,

			<&clock_mmss clk_camss_csi0_clk>,

			<&clock_mmss clk_camss_csi0_ahb_clk>,

			<&clock_mmss clk_csi0_clk_src>,

			<&clock_mmss clk_camss_csi0rdi_clk>,

			<&clock_mmss clk_camss_csi0pix_clk>,

			<&clock_mmss clk_camss_ahb_clk>;
@@ -106,7 +106,7 @@ 
			"ispif_ahb_clk", "csi_clk", "csi_ahb_clk",

			"csi_src_clk", "csi_rdi_clk",

			 "csi_pix_clk", "camss_ahb_clk";

		qcom,clock-rates = <0 0 0 0 240000000 0 0 0>;

		qcom,clock-rates = <0 0 240000000 0 0 0 0 0>;

	};



	qcom,csid@fda08400 {
@@ -121,9 +121,9 @@ 
		qcom,gdscr-vdd-supply = <&gdsc_camss_top>;

		clocks = <&clock_mmss clk_camss_top_ahb_clk>,

			<&clock_mmss clk_camss_ispif_ahb_clk>,

			<&clock_mmss clk_csi1_clk_src>,

			<&clock_mmss clk_camss_csi1_clk>,

			<&clock_mmss clk_camss_csi1_ahb_clk>,

			<&clock_mmss clk_csi1_clk_src>,

			<&clock_mmss clk_camss_csi1rdi_clk>,

			<&clock_mmss clk_camss_csi1pix_clk>,

			<&clock_mmss clk_camss_ahb_clk>;
@@ -131,7 +131,7 @@ 
			"ispif_ahb_clk", "csi_clk", "csi_ahb_clk",

			"csi_src_clk", "csi_rdi_clk",

			 "csi_pix_clk", "camss_ahb_clk";

		qcom,clock-rates = <0 0 0 0 240000000 0 0 0>;

		qcom,clock-rates = <0 0 240000000 0 0 0 0 0>;

	};



	qcom,csid@fda08800 {
@@ -146,9 +146,9 @@ 
		qcom,gdscr-vdd-supply = <&gdsc_camss_top>;

		clocks = <&clock_mmss clk_camss_top_ahb_clk>,

			<&clock_mmss clk_camss_ispif_ahb_clk>,

			<&clock_mmss clk_csi2_clk_src>,

			<&clock_mmss clk_camss_csi2_clk>,

			<&clock_mmss clk_camss_csi2_ahb_clk>,

			<&clock_mmss clk_csi2_clk_src>,

			<&clock_mmss clk_camss_csi2rdi_clk>,

			<&clock_mmss clk_camss_csi2pix_clk>,

			<&clock_mmss clk_camss_ahb_clk>;
@@ -156,7 +156,7 @@ 
			"ispif_ahb_clk", "csi_clk", "csi_ahb_clk",

			"csi_src_clk", "csi_rdi_clk",

			 "csi_pix_clk", "camss_ahb_clk";

		qcom,clock-rates = <0 0 0 0 240000000 0 0 0>;

		qcom,clock-rates = <0 0 240000000 0 0 0 0 0>;

	};



	qcom,csid@fda08c00 {
@@ -171,9 +171,9 @@ 
		qcom,gdscr-vdd-supply = <&gdsc_camss_top>;

		clocks = <&clock_mmss clk_camss_top_ahb_clk>,

			<&clock_mmss clk_camss_ispif_ahb_clk>,

			<&clock_mmss clk_csi3_clk_src>,

			<&clock_mmss clk_camss_csi3_clk>,

			<&clock_mmss clk_camss_csi3_ahb_clk>,

			<&clock_mmss clk_csi3_clk_src>,

			<&clock_mmss clk_camss_csi3rdi_clk>,

			<&clock_mmss clk_camss_csi3pix_clk>,

			<&clock_mmss clk_camss_ahb_clk>;
@@ -181,7 +181,7 @@ 
			"ispif_ahb_clk", "csi_clk", "csi_ahb_clk",

			"csi_src_clk", "csi_rdi_clk",

			 "csi_pix_clk", "camss_ahb_clk";

		qcom,clock-rates = <0 0 0 0 240000000 0 0 0>;

		qcom,clock-rates = <0 0 240000000 0 0 0 0 0>;

	};



	qcom,ispif@fda0a000 {