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Commit 0c7b4632 authored by Venkat Gopalakrishnan's avatar Venkat Gopalakrishnan
Browse files

mmc: sdhci: Poll for register status much tightly 



On fast path, waiting for 1ms interval to poll registers cause
performance degradation. Also having 1ms delays for polling with
interrupts disabled cause considerable system latencies, hence
poll at 1us interval.

Change-Id: I40113ccf56050b3c46604112846e9b37b254d2be
Signed-off-by: default avatarVenkat Gopalakrishnan <venkatg@codeaurora.org>
parent 2a9b24f2

drivers/mmc/host/sdhci.c

+6 −6
Original line number Diff line number Diff line
@@ -270,7 +270,7 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask) 
		host->clock = 0;



	/* Wait max 100 ms */

	timeout = 100;

	timeout = 100000;



	if (host->ops->check_power_status && host->pwr &&

	    (mask & SDHCI_RESET_ALL))
@@ -285,7 +285,7 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask) 
			return;

		}

		timeout--;

		mdelay(1);

		udelay(1);

	}



	if (host->ops->platform_reset_exit)
@@ -1159,7 +1159,7 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 
	WARN_ON(host->cmd);



	/* Wait max 10 ms */

	timeout = 10;

	timeout = 10000;



	mask = SDHCI_CMD_INHIBIT;

	if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
@@ -1180,7 +1180,7 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 
			return;

		}

		timeout--;

		mdelay(1);

		udelay(1);

	}



	mod_timer(&host->timer, jiffies + SDHCI_REQUEST_TIMEOUT * HZ);
@@ -1406,7 +1406,7 @@ clock_set: 
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);



	/* Wait max 20 ms */

	timeout = 20;

	timeout = 20000;

	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))

		& SDHCI_CLOCK_INT_STABLE)) {

		if (timeout == 0) {
@@ -1416,7 +1416,7 @@ clock_set: 
			goto ret;

		}

		timeout--;

		mdelay(1);

		udelay(1);

	}



	clk |= SDHCI_CLOCK_CARD_EN;