Loading drivers/platform/msm/ipa/ipa_ram_mmap.h +12 −8 Original line number Diff line number Diff line Loading @@ -269,11 +269,13 @@ #define IPA_MEM_v2_5_RAM_V4_RT_OFST (IPA_MEM_v2_5_RAM_V6_FLT_OFST + \ IPA_MEM_v2_5_RAM_V6_FLT_SIZE + 2 * IPA_MEM_CANARY_SIZE) #define IPA_MEM_v2_5_RAM_V4_NUM_INDEX 11 #define IPA_MEM_v2_5_RAM_V4_NUM_INDEX 15 #define IPA_MEM_v2_5_V4_MODEM_RT_INDEX_LO 0 #define IPA_MEM_v2_5_V4_MODEM_RT_INDEX_HI 3 #define IPA_MEM_v2_5_V4_APPS_RT_INDEX_LO 4 #define IPA_MEM_v2_5_V4_APPS_RT_INDEX_HI 10 #define IPA_MEM_v2_5_V4_MODEM_RT_INDEX_HI 6 #define IPA_MEM_v2_5_V4_APPS_RT_INDEX_LO \ (IPA_MEM_v2_5_V4_MODEM_RT_INDEX_HI + 1) #define IPA_MEM_v2_5_V4_APPS_RT_INDEX_HI \ (IPA_MEM_v2_5_RAM_V4_NUM_INDEX - 1) #define IPA_MEM_v2_5_RAM_V4_RT_SIZE (IPA_MEM_v2_5_RAM_V4_NUM_INDEX * 4) /* V4 routing header table is 8B aligned */ Loading @@ -283,11 +285,13 @@ #define IPA_MEM_v2_5_RAM_V6_RT_OFST (IPA_MEM_v2_5_RAM_V4_RT_OFST + \ IPA_MEM_v2_5_RAM_V4_RT_SIZE + IPA_MEM_CANARY_SIZE) #define IPA_MEM_v2_5_RAM_V6_NUM_INDEX 11 #define IPA_MEM_v2_5_RAM_V6_NUM_INDEX 15 #define IPA_MEM_v2_5_V6_MODEM_RT_INDEX_LO 0 #define IPA_MEM_v2_5_V6_MODEM_RT_INDEX_HI 3 #define IPA_MEM_v2_5_V6_APPS_RT_INDEX_LO 4 #define IPA_MEM_v2_5_V6_APPS_RT_INDEX_HI 10 #define IPA_MEM_v2_5_V6_MODEM_RT_INDEX_HI 6 #define IPA_MEM_v2_5_V6_APPS_RT_INDEX_LO \ (IPA_MEM_v2_5_V6_MODEM_RT_INDEX_HI + 1) #define IPA_MEM_v2_5_V6_APPS_RT_INDEX_HI \ (IPA_MEM_v2_5_RAM_V6_NUM_INDEX - 1) #define IPA_MEM_v2_5_RAM_V6_RT_SIZE (IPA_MEM_v2_5_RAM_V6_NUM_INDEX * 4) /* V6 routing header table is 8B aligned */ Loading Loading
drivers/platform/msm/ipa/ipa_ram_mmap.h +12 −8 Original line number Diff line number Diff line Loading @@ -269,11 +269,13 @@ #define IPA_MEM_v2_5_RAM_V4_RT_OFST (IPA_MEM_v2_5_RAM_V6_FLT_OFST + \ IPA_MEM_v2_5_RAM_V6_FLT_SIZE + 2 * IPA_MEM_CANARY_SIZE) #define IPA_MEM_v2_5_RAM_V4_NUM_INDEX 11 #define IPA_MEM_v2_5_RAM_V4_NUM_INDEX 15 #define IPA_MEM_v2_5_V4_MODEM_RT_INDEX_LO 0 #define IPA_MEM_v2_5_V4_MODEM_RT_INDEX_HI 3 #define IPA_MEM_v2_5_V4_APPS_RT_INDEX_LO 4 #define IPA_MEM_v2_5_V4_APPS_RT_INDEX_HI 10 #define IPA_MEM_v2_5_V4_MODEM_RT_INDEX_HI 6 #define IPA_MEM_v2_5_V4_APPS_RT_INDEX_LO \ (IPA_MEM_v2_5_V4_MODEM_RT_INDEX_HI + 1) #define IPA_MEM_v2_5_V4_APPS_RT_INDEX_HI \ (IPA_MEM_v2_5_RAM_V4_NUM_INDEX - 1) #define IPA_MEM_v2_5_RAM_V4_RT_SIZE (IPA_MEM_v2_5_RAM_V4_NUM_INDEX * 4) /* V4 routing header table is 8B aligned */ Loading @@ -283,11 +285,13 @@ #define IPA_MEM_v2_5_RAM_V6_RT_OFST (IPA_MEM_v2_5_RAM_V4_RT_OFST + \ IPA_MEM_v2_5_RAM_V4_RT_SIZE + IPA_MEM_CANARY_SIZE) #define IPA_MEM_v2_5_RAM_V6_NUM_INDEX 11 #define IPA_MEM_v2_5_RAM_V6_NUM_INDEX 15 #define IPA_MEM_v2_5_V6_MODEM_RT_INDEX_LO 0 #define IPA_MEM_v2_5_V6_MODEM_RT_INDEX_HI 3 #define IPA_MEM_v2_5_V6_APPS_RT_INDEX_LO 4 #define IPA_MEM_v2_5_V6_APPS_RT_INDEX_HI 10 #define IPA_MEM_v2_5_V6_MODEM_RT_INDEX_HI 6 #define IPA_MEM_v2_5_V6_APPS_RT_INDEX_LO \ (IPA_MEM_v2_5_V6_MODEM_RT_INDEX_HI + 1) #define IPA_MEM_v2_5_V6_APPS_RT_INDEX_HI \ (IPA_MEM_v2_5_RAM_V6_NUM_INDEX - 1) #define IPA_MEM_v2_5_RAM_V6_RT_SIZE (IPA_MEM_v2_5_RAM_V6_NUM_INDEX * 4) /* V6 routing header table is 8B aligned */ Loading