Merge "arm: Restore 64 bit TTBR0/TTBR1 registers for LPAE targets"

/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */

.globl	cpu_v7_suspend_size

.equ	cpu_v7_suspend_size, 4 * 8

.equ	cpu_v7_suspend_size, 4 * 9

#ifdef CONFIG_ARM_CPU_SUSPEND

ENTRY(cpu_v7_do_suspend)

	stmfd	sp!, {r4 - r10, lr}

	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID

	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID

	stmia	r0!, {r4 - r5}

	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID

#ifdef CONFIG_ARM_LPAE

	mrrc	p15, 1, r6, r7, c2	@ TTB 1

#else

	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1

#endif

	stmia	r0!,  {r4-r7}

	mrc	p15, 0, r7, c3, c0, 0	@ Domain ID

	mrc	p15, 0, r11, c2, c0, 2	@ TTB control register

	mrc	p15, 0, r8, c1, c0, 0	@ Control register

	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register

	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control

	stmia	r0, {r6 - r11}

	stmia	r0, {r7 - r11}

	ldmfd	sp!, {r4 - r10, pc}

ENDPROC(cpu_v7_do_suspend)

	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs

	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache

	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID

	ldmia	r0!, {r4 - r5}

	ldmia	r0!, {r4 - r7}

	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID

	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID

	ldmia	r0, {r6 - r11}

	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID

#ifndef CONFIG_ARM_LPAE

#ifdef CONFIG_ARM_LPAE

	mcrr	p15, 0, r1, ip, c2	@ TTB 0

	mcrr	p15, 1, r6, r7, c2	@ TTB 1

#else

	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)

	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)

#endif

	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0

	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1

#endif

	ldmia	r0!, {r7 - r11}

	mcr	p15, 0, r7, c3, c0, 0	@ Domain ID

	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register

	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register

	teq	r4, r9			@ Is it already set?