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Commit 0a397154 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-3.10-2' of git://people.freedesktop.org/~agd5f/linux into drm-next 

Alex writes:
A few more updates for 3.10.  Nothing too major here.  Mostly bug fixes.
The big changes are adding golden register init for 7xx and newer asics
and some audio cleanups.

* 'drm-next-3.10-2' of git://people.freedesktop.org/~agd5f/linux: (32 commits)
  drm/radeon: disable UVD advanced semaphore mode
  drm/radeon: fix endian bugs in radeon_atom_get_clock_dividers() (v3)
  drm/radeon: fix up audio dto programming for DCE2
  drm/radeon/evergreen: set SAD registers
  drm: add drm_edid_to_eld helper extracting SADs from EDID (v2)
  drm/radeon/si: add support for golden register init
  drm/radeon/cayman,TN: add support for golden register init (v2)
  drm/radeon/evergreen: add support for golden register init
  drm/radeon/7xx: add support for golden register init
  drm/radeon: add helper function to support golden registers
  drm/radeon: fix typo in si_select_se_sh()
  drm/radeon: switch audio handling to use callbacks
  drm/radeon: clean up audio dto programming
  drm/radeon: clean up audio supported check
  drm/radeon: raise UVD clocks on init v3
  drm/radeon: raise UVD clocks only on demand
  drm/radeon: put UVD PLLs in bypass mode
  drm/radeon: disable audio format interrupts on Evergreen
  drm/radeon: fix hdmi mode enable on RS600/RS690/RS740
  drm/radeon/evergreen: write default channel numbers
  ...
parents f9df7ea3 03708b05

drivers/gpu/drm/drm_edid.c

+59 −0
Original line number Diff line number Diff line
@@ -2510,6 +2510,65 @@ void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 
}

EXPORT_SYMBOL(drm_edid_to_eld);



/**

 * drm_edid_to_sad - extracts SADs from EDID

 * @edid: EDID to parse

 * @sads: pointer that will be set to the extracted SADs

 *

 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.

 * Note: returned pointer needs to be kfreed

 *

 * Return number of found SADs or negative number on error.

 */

int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)

{

	int count = 0;

	int i, start, end, dbl;

	u8 *cea;



	cea = drm_find_cea_extension(edid);

	if (!cea) {

		DRM_DEBUG_KMS("SAD: no CEA Extension found\n");

		return -ENOENT;

	}



	if (cea_revision(cea) < 3) {

		DRM_DEBUG_KMS("SAD: wrong CEA revision\n");

		return -ENOTSUPP;

	}



	if (cea_db_offsets(cea, &start, &end)) {

		DRM_DEBUG_KMS("SAD: invalid data block offsets\n");

		return -EPROTO;

	}



	for_each_cea_db(cea, i, start, end) {

		u8 *db = &cea[i];



		if (cea_db_tag(db) == AUDIO_BLOCK) {

			int j;

			dbl = cea_db_payload_len(db);



			count = dbl / 3; /* SAD is 3B */

			*sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);

			if (!*sads)

				return -ENOMEM;

			for (j = 0; j < count; j++) {

				u8 *sad = &db[1 + j * 3];



				(*sads)[j].format = (sad[0] & 0x78) >> 3;

				(*sads)[j].channels = sad[0] & 0x7;

				(*sads)[j].freq = sad[1] & 0x7F;

				(*sads)[j].byte2 = sad[2];

			}

			break;

		}

	}



	return count;

}

EXPORT_SYMBOL(drm_edid_to_sad);



/**

 * drm_av_sync_delay - HDMI/DP sink audio-video sync delay in millisecond

 * @connector: connector associated with the HDMI/DP sink

drivers/gpu/drm/radeon/atombios.h

+2 −0
Original line number Diff line number Diff line
@@ -458,6 +458,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 
  union

  {

    ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter

    ULONG ulClockParams;                      //ULONG access for BE

    ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter

  };

  UCHAR   ucRefDiv;                           //Output Parameter
@@ -490,6 +491,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 
  union

  {

    ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter

    ULONG ulClockParams;                      //ULONG access for BE

    ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter

  };

  UCHAR   ucRefDiv;                           //Output Parameter

drivers/gpu/drm/radeon/atombios_encoders.c

+8 −9
Original line number Diff line number Diff line
@@ -2150,13 +2150,10 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 
	atombios_apply_encoder_quirks(encoder, adjusted_mode);



	if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {

		r600_hdmi_enable(encoder);

		if (ASIC_IS_DCE6(rdev))

			; /* TODO (use pointers instead of if-s?) */

		else if (ASIC_IS_DCE4(rdev))

			evergreen_hdmi_setmode(encoder, adjusted_mode);

		else

			r600_hdmi_setmode(encoder, adjusted_mode);

		if (rdev->asic->display.hdmi_enable)

			radeon_hdmi_enable(rdev, encoder, true);

		if (rdev->asic->display.hdmi_setmode)

			radeon_hdmi_setmode(rdev, encoder, adjusted_mode);

	}

}
@@ -2413,8 +2410,10 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 


disable_done:

	if (radeon_encoder_is_digital(encoder)) {

		if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)

			r600_hdmi_disable(encoder);

		if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {

			if (rdev->asic->display.hdmi_enable)

				radeon_hdmi_enable(rdev, encoder, false);

		}

		dig = radeon_encoder->enc_priv;

		dig->dig_encoder = -1;

	}

drivers/gpu/drm/radeon/evergreen.c

+967 −19

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/radeon/evergreen_hdmi.c

+152 −17
Original line number Diff line number Diff line
@@ -54,6 +54,68 @@ static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t cloc 
	WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);

}



static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder)

{

	struct radeon_device *rdev = encoder->dev->dev_private;

	struct drm_connector *connector;

	struct radeon_connector *radeon_connector = NULL;

	struct cea_sad *sads;

	int i, sad_count;



	static const u16 eld_reg_to_type[][2] = {

		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },

		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },

		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },

		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },

		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },

		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },

		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },

		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },

		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },

		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },

		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },

		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },

	};



	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {

		if (connector->encoder == encoder)

			radeon_connector = to_radeon_connector(connector);

	}



	if (!radeon_connector) {

		DRM_ERROR("Couldn't find encoder's connector\n");

		return;

	}



	sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);

	if (sad_count < 0) {

		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);

		return;

	}

	BUG_ON(!sads);



	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {

		u32 value = 0;

		int j;



		for (j = 0; j < sad_count; j++) {

			struct cea_sad *sad = &sads[j];



			if (sad->format == eld_reg_to_type[i][1]) {

				value = MAX_CHANNELS(sad->channels) |

					DESCRIPTOR_BYTE_2(sad->byte2) |

					SUPPORTED_FREQUENCIES(sad->freq);

				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)

					value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq);

				break;

			}

		}

		WREG32(eld_reg_to_type[i][0], value);

	}



	kfree(sads);

}



/*

 * build a HDMI Video Info Frame

 */
@@ -85,6 +147,30 @@ static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, 
		frame[0xC] | (frame[0xD] << 8));

}



static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

	u32 base_rate = 48000;



	if (!dig || !dig->afmt)

		return;



	/* XXX: properly calculate this */

	/* XXX two dtos; generally use dto0 for hdmi */

	/* Express [24MHz / target pixel clock] as an exact rational

	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE

	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator

	 */

	WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff);

	WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff);

	WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));

}





/*

 * update the info frames with the data from the current display mode

 */
@@ -104,33 +190,19 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode 
		return;

	offset = dig->afmt->offset;



	r600_audio_set_clock(encoder, mode->clock);

	evergreen_audio_set_dto(encoder, mode->clock);



	WREG32(HDMI_VBI_PACKET_CONTROL + offset,

	       HDMI_NULL_SEND); /* send null packets when required */



	WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);



	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,

	       HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */

	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */



	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,

	       AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */

	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */



	WREG32(HDMI_ACR_PACKET_CONTROL + offset,

	       HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */

	       HDMI_ACR_SOURCE); /* select SW CTS value */



	WREG32(HDMI_VBI_PACKET_CONTROL + offset,

	       HDMI_NULL_SEND | /* send null packets when required */

	       HDMI_GC_SEND | /* send general control packets */

	       HDMI_GC_CONT); /* send general control packets every frame */



	WREG32(HDMI_INFOFRAME_CONTROL0 + offset,

	       HDMI_AVI_INFO_SEND | /* enable AVI info frames */

	       HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */

	       HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */

	       HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
@@ -138,11 +210,47 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode 
	       AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */



	WREG32(HDMI_INFOFRAME_CONTROL1 + offset,

	       HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */

	       HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */



	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */



	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,

	       HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */

	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */



	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,

	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */



	/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */



	WREG32(HDMI_ACR_PACKET_CONTROL + offset,

	       HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */

	       HDMI_ACR_SOURCE); /* select SW CTS value */



	evergreen_hdmi_update_ACR(encoder, mode->clock);



	WREG32(AFMT_60958_0 + offset,

	       AFMT_60958_CS_CHANNEL_NUMBER_L(1));



	WREG32(AFMT_60958_1 + offset,

	       AFMT_60958_CS_CHANNEL_NUMBER_R(2));



	WREG32(AFMT_60958_2 + offset,

	       AFMT_60958_CS_CHANNEL_NUMBER_2(3) |

	       AFMT_60958_CS_CHANNEL_NUMBER_3(4) |

	       AFMT_60958_CS_CHANNEL_NUMBER_4(5) |

	       AFMT_60958_CS_CHANNEL_NUMBER_5(6) |

	       AFMT_60958_CS_CHANNEL_NUMBER_6(7) |

	       AFMT_60958_CS_CHANNEL_NUMBER_7(8));



	/* fglrx sets 0x0001005f | (x & 0x00fc0000) in 0x5f78 here */



	WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,

	       AFMT_AUDIO_CHANNEL_ENABLE(0xff));



	/* fglrx sets 0x40 in 0x5f80 here */

	evergreen_hdmi_write_sad_regs(encoder);



	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);

	if (err < 0) {

		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
@@ -156,7 +264,17 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode 
	}



	evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));

	evergreen_hdmi_update_ACR(encoder, mode->clock);



	WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,

		  HDMI_AVI_INFO_SEND | /* enable AVI info frames */

		  HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */



	WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,

		 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */

		 ~HDMI_AVI_INFO_LINE_MASK);



	WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,

		  AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */



	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */

	WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
@@ -164,3 +282,20 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode 
	WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);

	WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);

}



void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)

{

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;



	/* Silent, r600_hdmi_enable will raise WARN for us */

	if (enable && dig->afmt->enabled)

		return;

	if (!enable && !dig->afmt->enabled)

		return;



	dig->afmt->enabled = enable;



	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",

		  enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);

}