Merge "qcom: clock-alpha-pll: Set a post divider if necessary" (08797e7d) · Commits · e / devices / android_kernel_sony_msm8994

drivers/clk/qcom/clock-alpha-pll.c

+8 −1

Original line number	Diff line number	Diff line
		@@ -33,6 +33,7 @@
		#define ALPHA_EN_REG(pll) (*pll->base + pll->offset + 0x10)
		#define OUTPUT_REG(pll) (*pll->base + pll->offset + 0x10)
		#define VOTE_REG(pll) (*pll->base + pll->fsm_reg_offset)
		#define USER_CTL_LO_REG(pll) (*pll->base + pll->offset + 0x10)

		#define PLL_BYPASSNL 0x2
		#define PLL_RESET_N 0x4
		@@ -396,7 +397,7 @@ static enum handoff alpha_pll_handoff(struct clk *c)
		struct alpha_pll_masks *masks = pll->masks;
		u64 a_val;
		u32 alpha_en, l_val;
		u32 output_en;
		u32 output_en, userval;

		update_vco_tbl(pll);

		@@ -409,6 +410,12 @@ static enum handoff alpha_pll_handoff(struct clk *c)
		output_en \|= pll->enable_config;
		writel_relaxed(output_en, OUTPUT_REG(pll));
		}
		if (masks->post_div_mask) {
		userval = readl_relaxed(USER_CTL_LO_REG(pll));
		userval &= ~masks->post_div_mask;
		userval \|= pll->post_div_config;
		writel_relaxed(userval, USER_CTL_LO_REG(pll));
		}
		if (pll->fsm_en_mask)
		__set_fsm_mode(MODE_REG(pll));
		return HANDOFF_DISABLED_CLK;

+2 −0

Original line number	Diff line number	Diff line
		@@ -737,6 +737,7 @@ static struct alpha_pll_masks alpha_pll_masks_20nm_p = {
		.vco_shift = 20,
		.alpha_en_mask = BIT(24),
		.output_mask = 0xF,
		.post_div_mask = 0xF00,
		};

		static struct alpha_pll_vco_tbl alpha_pll_vco_20nm_p[] = {
		@@ -749,6 +750,7 @@ static struct alpha_pll_clk cci_pll = {
		.vco_tbl = alpha_pll_vco_20nm_p,
		.num_vco = ARRAY_SIZE(alpha_pll_vco_20nm_p),
		.enable_config = 0x9, /* Main and early outputs */
		.post_div_config = 0x100, /* Div-2 */
		.c = {
		.parent = &xo_ao.c,
		.dbg_name = "cci_pll",

+2 −0

Original line number	Diff line number	Diff line
		@@ -26,6 +26,7 @@ struct alpha_pll_masks {
		u32 vco_shift;
		u32 alpha_en_mask; /* alpha_en bit */
		u32 output_mask; /* pllout_* bits */
		u32 post_div_mask;
		};

		struct alpha_pll_vco_tbl {
		@@ -50,6 +51,7 @@ struct alpha_pll_clk {
		const u32 fsm_en_mask;

		u32 enable_config; /* bitmask of outputs to be enabled */
		u32 post_div_config; /* masked post divider setting */

		struct alpha_pll_vco_tbl *vco_tbl;
		u32 num_vco;