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Commit 05f19199 authored by Stepan Moskovchenko's avatar Stepan Moskovchenko
Browse files

ARM: dts: msm: Add MSM8992 support 



Add the device tree files needed to describe the hardware
on the MSM8992 Sim and Rumi platforms.

Change-Id: I38411eb1e4475e2663a43c1f07663640b5071e15
Signed-off-by: default avatarStepan Moskovchenko <stepanm@codeaurora.org>
parent 21f25e45

arch/arm/boot/dts/qcom/msm8992-pinctrl.dtsi

0 → 100644
+47 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	tlmm_pinmux: pinctrl@fd510000 {

		compatible = "qcom,msm-tlmm-8994", "qcom,msm-tlmm-8974";

		reg = <0xfd510000 0x4000>;

		interrupts = <0 208 0>;



		/*General purpose pins*/

		gp: gp {

			qcom,num-pins = <146>;

			#qcom,pin-cells = <1>;



			msm_gpio: msm_gpio {

				compatible = "qcom,msm-tlmm-gp";

				gpio-controller;

				#gpio-cells = <2>;

				interrupt-controller;

				#interrupt-cells = <2>;

				qcom,direct-connect-irqs = <8>;

				num_irqs = <146>;

			};

		};



		pmx-uartconsole {

			qcom,pins = <&gp 4>, <&gp 5>;

			qcom,num-grp-pins = <2>;

			qcom,pin-func = <2>;

			label = "uart-console";



		uart_console_sleep: uart-console {

				drive-strength = <2>;

				bias-pull-down;

			};

		};

	};

};

arch/arm/boot/dts/qcom/msm8992-rumi.dts

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+29 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */





/dts-v1/;



/memreserve/ 0x06000000 0x00001000;



#include "msm8992.dtsi"

#include "msm8992-pinctrl.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. Technologies, Inc. MSM8992 RUMI";

	compatible = "qcom,msm8992-rumi", "qcom,msm8992", "qcom,rumi";

	qcom,board-id = <15 0>;

};



&blsp1_uart5 {

	status = "ok";

};

arch/arm/boot/dts/qcom/msm8992-sim.dts

0 → 100644
+29 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */





/dts-v1/;



/memreserve/ 0x06000000 0x00001000;



#include "msm8992.dtsi"

#include "msm8992-pinctrl.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. MSM 8992SIM";

	compatible = "qcom,msm8992-sim", "qcom,msm8992", "qcom,sim";

	qcom,board-id = <16 0>;

};



&blsp1_uart2 {

	status = "ok";

};

arch/arm/boot/dts/qcom/msm8992.dtsi

0 → 100644
+236 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include "skeleton64.dtsi"

#include <dt-bindings/clock/msm-clocks-8994.h>



/ {

	model = "Qualcomm Technologies, Inc. MSM 8992";

	compatible = "qcom,msm8992";

	qcom,msm-id = <251 0>, <252 0>;

	interrupt-parent = <&intc>;



	aliases {

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU0>;

				};

				core1 {

					cpu = <&CPU1>;

				};

				core2 {

					cpu = <&CPU2>;

				};

				core3 {

					cpu = <&CPU3>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&CPU4>;

				};

				core1 {

					cpu = <&CPU5>;

				};

			};

		};



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x06000000>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			};

		};



		CPU1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x1>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x06000000>;

			next-level-cache = <&L2_0>;

		};



		CPU2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x2>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x06000000>;

			next-level-cache = <&L2_0>;

		};



		CPU3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x3>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x06000000>;

			next-level-cache = <&L2_0>;

		};



		CPU4: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x100>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x06000000>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			};

		};



		CPU5: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x101>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x06000000>;

			next-level-cache = <&L2_1>;

		};

	};



	soc: soc { };



	memory {

		#address-cells = <2>;

		#size-cells = <2>;

	};

};



&soc {

	#address-cells = <1>;

	#size-cells = <1>;

	ranges = <0 0 0 0xffffffff>;

	compatible = "simple-bus";



	intc: interrupt-controller@f9000000 {

		compatible = "qcom,msm-qgic2";

		interrupt-controller;

		#interrupt-cells = <3>;

		reg = <0xf9000000 0x1000>,

		      <0xf9002000 0x1000>;

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <1 2 0xf08>,

			     <1 3 0xf08>,

			     <1 4 0xf08>,

			     <1 1 0xf08>;

		clock-frequency = <19200000>;

	};



	timer@f9020000 {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		compatible = "arm,armv7-timer-mem";

		reg = <0xf9020000 0x1000>;

		clock-frequency = <19200000>;



		frame@f9021000 {

			frame-number = <0>;

			interrupts = <0 9 0x4>,

				     <0 8 0x4>;

			reg = <0xf9021000 0x1000>,

			      <0xf9022000 0x1000>;

		};



		frame@f9023000 {

			frame-number = <1>;

			interrupts = <0 10 0x4>;

			reg = <0xf9023000 0x1000>;

			status = "disabled";

		};



		frame@f9024000 {

			frame-number = <2>;

			interrupts = <0 11 0x4>;

			reg = <0xf9024000 0x1000>;

			status = "disabled";

		};



		frame@f9025000 {

			frame-number = <3>;

			interrupts = <0 12 0x4>;

			reg = <0xf9025000 0x1000>;

			status = "disabled";

		};



		frame@f9026000 {

			frame-number = <4>;

			interrupts = <0 13 0x4>;

			reg = <0xf9026000 0x1000>;

			status = "disabled";

		};



		frame@f9027000 {

			frame-number = <5>;

			interrupts = <0 14 0x4>;

			reg = <0xf9027000 0x1000>;

			status = "disabled";

		};



		frame@f9028000 {

			frame-number = <6>;

			interrupts = <0 15 0x4>;

			reg = <0xf9028000 0x1000>;

			status = "disabled";

		};

	};



	restart@fc4ab000 {

		compatible = "qcom,pshold";

		reg = <0xfc4ab000 0x4>;

	};



	blsp1_uart2: serial@f991e000 {

		compatible = "qcom,msm-lsuart-v14";

		reg = <0xf991e000 0x1000>;

		interrupts = <0 108 0>;

		status = "disabled";

                clock-names = "core_clk", "iface_clk";

                clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,

			 <&clock_gcc clk_gcc_blsp1_ahb_clk>;

	};



	blsp1_uart5: serial@f9922000 {

		compatible = "qcom,msm-lsuart-v14";

		reg = <0xf9922000 0x1000>;

		interrupts = <0 112 0>;

		status = "disabled";

		clock-names = "core_clk", "iface_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,

			 <&clock_gcc clk_gcc_blsp1_ahb_clk>;

	};



	clock_gcc: qcom,gcc@fc400000 {

		compatible = "qcom,dummycc";

		#clock-cells = <1>;

	};

};