Loading drivers/soc/qcom/pil-q6v5.c +5 −0 Original line number Diff line number Diff line Loading @@ -67,6 +67,7 @@ #define QDSP6v55_LDO_BYP BIT(25) #define QDSP6v55_BHS_ON BIT(24) #define QDSP6v55_CLAMP_WL BIT(21) #define QDSP6v55_CLAMP_QMC_MEM BIT(22) #define L1IU_SLP_NRET_N BIT(15) #define L1DU_SLP_NRET_N BIT(14) #define L2PLRU_SLP_NRET_N BIT(13) Loading Loading @@ -369,6 +370,10 @@ static int __pil_q6v55_reset(struct pil_desc *pil) val &= ~Q6SS_CLAMP_IO; writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL); /* Remove QMC_MEM clamp */ val &= ~QDSP6v55_CLAMP_QMC_MEM; writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL); /* Bring core out of reset */ val = readl_relaxed(drv->reg_base + QDSP6SS_RESET); val &= ~(Q6SS_CORE_ARES | Q6SS_STOP_CORE); Loading Loading
drivers/soc/qcom/pil-q6v5.c +5 −0 Original line number Diff line number Diff line Loading @@ -67,6 +67,7 @@ #define QDSP6v55_LDO_BYP BIT(25) #define QDSP6v55_BHS_ON BIT(24) #define QDSP6v55_CLAMP_WL BIT(21) #define QDSP6v55_CLAMP_QMC_MEM BIT(22) #define L1IU_SLP_NRET_N BIT(15) #define L1DU_SLP_NRET_N BIT(14) #define L2PLRU_SLP_NRET_N BIT(13) Loading Loading @@ -369,6 +370,10 @@ static int __pil_q6v55_reset(struct pil_desc *pil) val &= ~Q6SS_CLAMP_IO; writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL); /* Remove QMC_MEM clamp */ val &= ~QDSP6v55_CLAMP_QMC_MEM; writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL); /* Bring core out of reset */ val = readl_relaxed(drv->reg_base + QDSP6SS_RESET); val &= ~(Q6SS_CORE_ARES | Q6SS_STOP_CORE); Loading