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Commit 025ef33a authored by Tony Truong's avatar Tony Truong
Browse files

msm: pcie: make AUX and core clock to be asynchronous 



AUX clock and core clock should be asynchronous unless L1ss
is supported and aux_clk_sync is not defined in devicetree.

Change-Id: Id448674c1c157e222bb62d6a680f9acef157d8ee
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent 82194ced

drivers/pci/host/pci-msm.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -2499,7 +2499,7 @@ int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) 
	/* change DBI base address */

	/* change DBI base address */

	writel_relaxed(0, dev->parf + PCIE20_PARF_DBI_BASE_ADDR);

	writel_relaxed(0, dev->parf + PCIE20_PARF_DBI_BASE_ADDR);





	writel_relaxed(0x3656, dev->parf + PCIE20_PARF_SYS_CTRL);

	writel_relaxed(0x365E, dev->parf + PCIE20_PARF_SYS_CTRL);





	if (dev->dev_mem_res->end - dev->dev_mem_res->start > SZ_8M)

	if (dev->dev_mem_res->end - dev->dev_mem_res->start > SZ_8M)

		writel_relaxed(SZ_16M, dev->parf +

		writel_relaxed(SZ_16M, dev->parf +