Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ff9bd2d8 authored by Sven Eckelmann's avatar Sven Eckelmann Committed by John W. Linville
Browse files

ath9k_hw: Handle AR_INTR_SYNC_HOST1_(FATAL|PERR) on AR9003 



Interrupts with the sync_cause AR_INTR_SYNC_HOST1_FATAL and
AR_INTR_SYNC_HOST1_PERR have to be handled using a chip reset. Otherwise a
interrupt storm with unhandled interrupts will cause a hang or crash of the
machine.

Signed-off-by: default avatarSven Eckelmann <sven@narfation.org>
Signed-off-by: default avatarSimon Wunderlich <siwu@hrz.tu-chemnitz.de>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 6c8c4f72

drivers/net/wireless/ath/ath9k/ar9003_mac.c

+17 −0
Original line number Original line Diff line number Diff line
@@ -182,6 +182,7 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) 
	struct ath9k_hw_capabilities *pCap = &ah->caps;

	struct ath9k_hw_capabilities *pCap = &ah->caps;

	struct ath_common *common = ath9k_hw_common(ah);

	struct ath_common *common = ath9k_hw_common(ah);

	u32 sync_cause = 0, async_cause, async_mask = AR_INTR_MAC_IRQ;

	u32 sync_cause = 0, async_cause, async_mask = AR_INTR_MAC_IRQ;

	bool fatal_int;





	if (ath9k_hw_mci_is_enabled(ah))

	if (ath9k_hw_mci_is_enabled(ah))

		async_mask |= AR_INTR_ASYNC_MASK_MCI;

		async_mask |= AR_INTR_ASYNC_MASK_MCI;
@@ -310,6 +311,22 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) 




	if (sync_cause) {

	if (sync_cause) {

		ath9k_debug_sync_cause(common, sync_cause);

		ath9k_debug_sync_cause(common, sync_cause);

		fatal_int =

			(sync_cause &

			 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))

			? true : false;



		if (fatal_int) {

			if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {

				ath_dbg(common, ANY,

					"received PCI FATAL interrupt\n");

			}

			if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {

				ath_dbg(common, ANY,

					"received PCI PERR interrupt\n");

			}

			*masked |= ATH9K_INT_FATAL;

		}





		if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {

		if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {

			REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);

			REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);