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Commit fc58acdb authored by Jerome Glisse's avatar Jerome Glisse Committed by Alex Deucher
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radeon: fix pll/ctrc mapping on dce2 and dce3 hardware 



This fix black screen on resume issue that some people are
experiencing. There is a bug in the atombios code regarding
pll/crtc mapping. The atombios code reverse the logic for
the pll and crtc mapping.

agd5f: drop unnecessary crtc id check, cc stable in case
we miss 3.7.

This fixes the root cause that was worked around by commits:
drm/radeon: allocate PPLLs from low to high
drm/radeon/dce3: switch back to old pll allocation order for discrete

Signed-off-by: default avatarJerome Glisse <jglisse@redhat.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 452f1920

drivers/gpu/drm/radeon/atombios_crtc.c

+14 −34
Original line number Original line Diff line number Diff line
@@ -1696,42 +1696,22 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
			return ATOM_PPLL2;

			return ATOM_PPLL2;

		DRM_ERROR("unable to allocate a PPLL\n");

		DRM_ERROR("unable to allocate a PPLL\n");

		return ATOM_PPLL_INVALID;

		return ATOM_PPLL_INVALID;

	} else if (ASIC_IS_AVIVO(rdev)) {

		/* in DP mode, the DP ref clock can come from either PPLL

		 * depending on the asic:

		 * DCE3: PPLL1 or PPLL2

		 */

		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {

			/* use the same PPLL for all DP monitors */

			pll = radeon_get_shared_dp_ppll(crtc);

			if (pll != ATOM_PPLL_INVALID)

				return pll;

		} else {

			/* use the same PPLL for all monitors with the same clock */

			pll = radeon_get_shared_nondp_ppll(crtc);

			if (pll != ATOM_PPLL_INVALID)

				return pll;

		}

		/* all other cases */

		pll_in_use = radeon_get_pll_use_mask(crtc);

		/* the order shouldn't matter here, but we probably

		 * need this until we have atomic modeset

		 */

		if (rdev->flags & RADEON_IS_IGP) {

			if (!(pll_in_use & (1 << ATOM_PPLL1)))

				return ATOM_PPLL1;

			if (!(pll_in_use & (1 << ATOM_PPLL2)))

				return ATOM_PPLL2;

		} else {

			if (!(pll_in_use & (1 << ATOM_PPLL2)))

				return ATOM_PPLL2;

			if (!(pll_in_use & (1 << ATOM_PPLL1)))

				return ATOM_PPLL1;

		}

		DRM_ERROR("unable to allocate a PPLL\n");

		return ATOM_PPLL_INVALID;

	} else {

	} else {

		/* on pre-R5xx asics, the crtc to pll mapping is hardcoded */

		/* on pre-R5xx asics, the crtc to pll mapping is hardcoded */

		/* some atombios (observed in some DCE2/DCE3) code have a bug,

		 * the matching btw pll and crtc is done through

		 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the

		 * pll (1 or 2) to select which register to write. ie if using

		 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2

		 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to

		 * choose which value to write. Which is reverse order from

		 * register logic. So only case that works is when pllid is

		 * same as crtcid or when both pll and crtc are enabled and

		 * both use same clock.

		 *

		 * So just return crtc id as if crtc and pll were hard linked

		 * together even if they aren't

		 */

		return radeon_crtc->crtc_id;

		return radeon_crtc->crtc_id;

	}

	}

}

}