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Commit f5178ddd authored by Nicolas Pitre's avatar Nicolas Pitre
Browse files

ARM: PJ4: remove the ARMv6 compatible cache method entries 



The Marvell PJ4 is ARMv7 capable, so we don't support it in
ARMv6 mode anymore.

Signed-off-by: default avatarNicolas Pitre <nico@fluxnic.net>
Acked-by: default avatarSaeed Bishara <saeed.bishara@gmail.com>
Acked-by: default avatarHaojian Zhuang <haojian.zhuang@gmail.com>
parent 0ffd3c48

arch/arm/boot/compressed/head.S

+0 −6
Original line number Diff line number Diff line
@@ -735,12 +735,6 @@ proc_types: 
		W(b)	__armv4_mmu_cache_off

		W(b)	__armv6_mmu_cache_flush



		.word	0x560f5810		@ Marvell PJ4 ARMv6

		.word	0xff0ffff0

		W(b)	__armv4_mmu_cache_on

		W(b)	__armv4_mmu_cache_off

		W(b)	__armv6_mmu_cache_flush



		.word	0x000f0000		@ new CPU Id

		.word	0x000f0000

		W(b)	__armv7_mmu_cache_on

arch/arm/mm/proc-v6.S

+0 −34
Original line number Diff line number Diff line
@@ -175,11 +175,6 @@ cpu_v6_name: 
	.asciz	"ARMv6-compatible processor"

	.size	cpu_v6_name, . - cpu_v6_name



	.type	cpu_pj4_name, #object

cpu_pj4_name:

	.asciz	"Marvell PJ4 processor"

	.size	cpu_pj4_name, . - cpu_pj4_name



	.align



	__CPUINIT
@@ -305,32 +300,3 @@ __v6_proc_info: 
	.long	v6_user_fns

	.long	v6_cache_fns

	.size	__v6_proc_info, . - __v6_proc_info
 


	.type	__pj4_v6_proc_info, #object

__pj4_v6_proc_info:

	.long	0x560f5810

	.long	0xff0ffff0

	ALT_SMP(.long \

		PMD_TYPE_SECT | \

		PMD_SECT_AP_WRITE | \

		PMD_SECT_AP_READ | \

		PMD_FLAGS_SMP)

	ALT_UP(.long \

		PMD_TYPE_SECT | \

		PMD_SECT_AP_WRITE | \

		PMD_SECT_AP_READ | \

		PMD_FLAGS_UP)

	.long   PMD_TYPE_SECT | \

		PMD_SECT_XN | \

		PMD_SECT_AP_WRITE | \

		PMD_SECT_AP_READ

	b	__v6_setup

	.long	cpu_arch_name

	.long	cpu_elf_name

	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS

	.long	cpu_pj4_name

	.long	v6_processor_functions

	.long	v6wbi_tlb_fns

	.long	v6_user_fns

	.long	v6_cache_fns

	.size	__pj4_v6_proc_info, . - __pj4_v6_proc_info