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Commit f447ed2d authored by Josh Cartwright's avatar Josh Cartwright Committed by Michal Simek
Browse files

zynq: use GIC device tree bindings 



The Zynq uses the cortex-a9-gic.  This eliminates the need to hardcode
register addresses.

Signed-off-by: default avatarJosh Cartwright <josh.cartwright@ni.com>
Cc: John Linn <john.linn@xilinx.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Tested-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent 8f0d8163

arch/arm/boot/dts/zynq-ep107.dts

+6 −4
Original line number Diff line number Diff line
@@ -36,16 +36,18 @@ 
		ranges;



		intc: interrupt-controller@f8f01000 {

			compatible = "arm,cortex-a9-gic";

			#interrupt-cells = <3>;

			#address-cells = <1>;

			interrupt-controller;

			compatible = "arm,gic";

			reg = <0xF8F01000 0x1000>;

			#interrupt-cells = <2>;

			reg = <0xF8F01000 0x1000>,

			      <0xF8F00100 0x100>;

		};



		uart0: uart@e0000000 {

			compatible = "xlnx,xuartps";

			reg = <0xE0000000 0x1000>;

			interrupts = <59 0>;

			interrupts = <0 27 4>;

			clock = <50000000>;

		};

	};

arch/arm/mach-zynq/common.c

+6 −1
Original line number Diff line number Diff line
@@ -55,12 +55,17 @@ static void __init xilinx_init_machine(void) 
	of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL);

}



static struct of_device_id irq_match[] __initdata = {

	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },

	{ }

};



/**

 * xilinx_irq_init() - Interrupt controller initialization for the GIC.

 */

static void __init xilinx_irq_init(void)

{

	gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE);

	of_irq_init(irq_match);

}



/* The minimum devices needed to be mapped before the VM system is up and

arch/arm/mach-zynq/include/mach/zynq_soc.h

+0 −2
Original line number Diff line number Diff line
@@ -35,8 +35,6 @@ 


#define TTC0_BASE			IOMEM(TTC0_VIRT)

#define SCU_PERIPH_BASE			IOMEM(SCU_PERIPH_VIRT)

#define SCU_GIC_CPU_BASE		(SCU_PERIPH_BASE + 0x100)

#define SCU_GIC_DIST_BASE		(SCU_PERIPH_BASE + 0x1000)

#define PL310_L2CC_BASE			IOMEM(PL310_L2CC_VIRT)



/*