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Commit e839ca52 authored by David Howells's avatar David Howells
Browse files

Disintegrate asm/system.h for SH 



Disintegrate asm/system.h for SH.

Signed-off-by: default avatarDavid Howells <dhowells@redhat.com>
cc: linux-sh@vger.kernel.org
parent 4eb14db4

arch/sh/boards/mach-microdev/irq.c

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@@ -12,7 +12,6 @@ 
#include <linux/init.h>

#include <linux/irq.h>

#include <linux/interrupt.h>

#include <asm/system.h>

#include <asm/io.h>

#include <mach/microdev.h>

arch/sh/include/asm/atomic-irq.h

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#ifndef __ASM_SH_ATOMIC_IRQ_H

#define __ASM_SH_ATOMIC_IRQ_H



#include <linux/irqflags.h>



/*

 * To get proper branch prediction for the main line, we must branch

 * forward to code at the end of this object's .text section, then

arch/sh/include/asm/atomic.h

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@@ -9,7 +9,7 @@ 


#include <linux/compiler.h>

#include <linux/types.h>

#include <asm/system.h>

#include <asm/cmpxchg.h>



#define ATOMIC_INIT(i)	( (atomic_t) { (i) } )

arch/sh/include/asm/auxvec.h

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@@ -33,4 +33,6 @@ 
#define AT_L1D_CACHESHAPE	35

#define AT_L2_CACHESHAPE	36



#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */



#endif /* __ASM_SH_AUXVEC_H */

arch/sh/include/asm/barrier.h

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/*

 * Copyright (C) 1999, 2000  Niibe Yutaka  &  Kaz Kojima

 * Copyright (C) 2002 Paul Mundt

 */

#ifndef __ASM_SH_BARRIER_H

#define __ASM_SH_BARRIER_H



#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)

#include <asm/cache_insns.h>

#endif



/*

 * A brief note on ctrl_barrier(), the control register write barrier.

 *

 * Legacy SH cores typically require a sequence of 8 nops after

 * modification of a control register in order for the changes to take

 * effect. On newer cores (like the sh4a and sh5) this is accomplished

 * with icbi.

 *

 * Also note that on sh4a in the icbi case we can forego a synco for the

 * write barrier, as it's not necessary for control registers.

 *

 * Historically we have only done this type of barrier for the MMUCR, but

 * it's also necessary for the CCR, so we make it generic here instead.

 */

#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)

#define mb()		__asm__ __volatile__ ("synco": : :"memory")

#define rmb()		mb()

#define wmb()		__asm__ __volatile__ ("synco": : :"memory")

#define ctrl_barrier()	__icbi(PAGE_OFFSET)

#define read_barrier_depends()	do { } while(0)

#else

#define mb()		__asm__ __volatile__ ("": : :"memory")

#define rmb()		mb()

#define wmb()		__asm__ __volatile__ ("": : :"memory")

#define ctrl_barrier()	__asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")

#define read_barrier_depends()	do { } while(0)

#endif



#ifdef CONFIG_SMP

#define smp_mb()	mb()

#define smp_rmb()	rmb()

#define smp_wmb()	wmb()

#define smp_read_barrier_depends()	read_barrier_depends()

#else

#define smp_mb()	barrier()

#define smp_rmb()	barrier()

#define smp_wmb()	barrier()

#define smp_read_barrier_depends()	do { } while(0)

#endif



#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)



#endif /* __ASM_SH_BARRIER_H */