Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e7d7cad0 authored by Jani Nikula's avatar Jani Nikula Committed by Daniel Vetter
Browse files

drm/i915/dsi: clean up MIPI DSI pipe vs. port usage 



MIPI DSI works on ports A and C, which map to pipes A and B,
respectively. Things are going to get more complicated with the
introduction of dual link DSI support, so clean up the register defines
and code to match reality.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarGaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 1362b776

drivers/gpu/drm/i915/i915_reg.h

+153 −150
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ 
#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))

#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \

			       (pipe) == PIPE_B ? (b) : (c))

#define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \

			       (port) == PORT_B ? (b) : (c))



#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))

#define _MASKED_BIT_DISABLE(a) ((a) << 16)
@@ -1494,7 +1496,7 @@ enum punit_power_well { 
#define I915_ISP_INTERRUPT				(1<<22)

#define I915_LPE_PIPE_B_INTERRUPT			(1<<21)

#define I915_LPE_PIPE_A_INTERRUPT			(1<<20)

#define I915_MIPIB_INTERRUPT				(1<<19)

#define I915_MIPIC_INTERRUPT				(1<<19)

#define I915_MIPIA_INTERRUPT				(1<<18)

#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)

#define I915_DISPLAY_PORT_INTERRUPT			(1<<17)
@@ -6652,29 +6654,30 @@ enum punit_power_well { 
#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)

#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)



/* VLV MIPI registers */

/* MIPI DSI registers */



#define _MIPI_PORT(port, a, c)	_PORT3(port, a, 0, c)	/* ports A and C only */



#define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)

#define _MIPIB_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)

#define MIPI_PORT_CTRL(tc)		_TRANSCODER(tc, _MIPIA_PORT_CTRL, \

						_MIPIB_PORT_CTRL)

#define  DPI_ENABLE					(1 << 31) /* A + B */

#define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)

#define MIPI_PORT_CTRL(port)	_MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)

#define  DPI_ENABLE					(1 << 31) /* A + C */

#define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27

#define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)

#define  DUAL_LINK_MODE_MASK				(1 << 26)

#define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)

#define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)

#define  DITHERING_ENABLE				(1 << 25) /* A + B */

#define  DITHERING_ENABLE				(1 << 25) /* A + C */

#define  FLOPPED_HSTX					(1 << 23)

#define  DE_INVERT					(1 << 19) /* XXX */

#define  MIPIA_FLISDSI_DELAY_COUNT_SHIFT		18

#define  MIPIA_FLISDSI_DELAY_COUNT_MASK			(0xf << 18)

#define  AFE_LATCHOUT					(1 << 17)

#define  LP_OUTPUT_HOLD					(1 << 16)

#define  MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT		15

#define  MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK		(1 << 15)

#define  MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT		11

#define  MIPIB_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 11)

#define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT		15

#define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK		(1 << 15)

#define  MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT		11

#define  MIPIC_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 11)

#define  CSB_SHIFT					9

#define  CSB_MASK					(3 << 9)

#define  CSB_20MHZ					(0 << 9)
@@ -6683,10 +6686,10 @@ enum punit_power_well { 
#define  BANDGAP_MASK					(1 << 8)

#define  BANDGAP_PNW_CIRCUIT				(0 << 8)

#define  BANDGAP_LNC_CIRCUIT				(1 << 8)

#define  MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT		5

#define  MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK		(7 << 5)

#define  TEARING_EFFECT_DELAY				(1 << 4) /* A + B */

#define  TEARING_EFFECT_SHIFT				2 /* A + B */

#define  MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT		5

#define  MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK		(7 << 5)

#define  TEARING_EFFECT_DELAY				(1 << 4) /* A + C */

#define  TEARING_EFFECT_SHIFT				2 /* A + C */

#define  TEARING_EFFECT_MASK				(3 << 2)

#define  TEARING_EFFECT_OFF				(0 << 2)

#define  TEARING_EFFECT_DSI				(1 << 2)
@@ -6698,9 +6701,9 @@ enum punit_power_well { 
#define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)



#define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)

#define _MIPIB_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)

#define MIPI_TEARING_CTRL(tc)			_TRANSCODER(tc, \

				_MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL)

#define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)

#define MIPI_TEARING_CTRL(port)			_MIPI_PORT(port, \

				_MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)

#define  TEARING_EFFECT_DELAY_SHIFT			0

#define  TEARING_EFFECT_DELAY_MASK			(0xffff << 0)
@@ -6710,9 +6713,9 @@ enum punit_power_well { 
/* MIPI DSI Controller and D-PHY registers */



#define _MIPIA_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb000)

#define _MIPIB_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb800)

#define MIPI_DEVICE_READY(tc)		_TRANSCODER(tc, _MIPIA_DEVICE_READY, \

						_MIPIB_DEVICE_READY)

#define _MIPIC_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb800)

#define MIPI_DEVICE_READY(port)		_MIPI_PORT(port, _MIPIA_DEVICE_READY, \

						_MIPIC_DEVICE_READY)

#define  BUS_POSSESSION					(1 << 3) /* set to give bus to receiver */

#define  ULPS_STATE_MASK				(3 << 1)

#define  ULPS_STATE_ENTER				(2 << 1)
@@ -6721,13 +6724,13 @@ enum punit_power_well { 
#define  DEVICE_READY					(1 << 0)



#define _MIPIA_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb004)

#define _MIPIB_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb804)

#define MIPI_INTR_STAT(tc)		_TRANSCODER(tc, _MIPIA_INTR_STAT, \

					_MIPIB_INTR_STAT)

#define _MIPIC_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb804)

#define MIPI_INTR_STAT(port)		_MIPI_PORT(port, _MIPIA_INTR_STAT, \

					_MIPIC_INTR_STAT)

#define _MIPIA_INTR_EN			(dev_priv->mipi_mmio_base + 0xb008)

#define _MIPIB_INTR_EN			(dev_priv->mipi_mmio_base + 0xb808)

#define MIPI_INTR_EN(tc)		_TRANSCODER(tc, _MIPIA_INTR_EN, \

					_MIPIB_INTR_EN)

#define _MIPIC_INTR_EN			(dev_priv->mipi_mmio_base + 0xb808)

#define MIPI_INTR_EN(port)		_MIPI_PORT(port, _MIPIA_INTR_EN, \

					_MIPIC_INTR_EN)

#define  TEARING_EFFECT					(1 << 31)

#define  SPL_PKT_SENT_INTERRUPT				(1 << 30)

#define  GEN_READ_DATA_AVAIL				(1 << 29)
@@ -6762,9 +6765,9 @@ enum punit_power_well { 
#define  RXSOT_ERROR					(1 << 0)



#define _MIPIA_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb00c)

#define _MIPIB_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb80c)

#define MIPI_DSI_FUNC_PRG(tc)		_TRANSCODER(tc, _MIPIA_DSI_FUNC_PRG, \

						_MIPIB_DSI_FUNC_PRG)

#define _MIPIC_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb80c)

#define MIPI_DSI_FUNC_PRG(port)		_MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \

						_MIPIC_DSI_FUNC_PRG)

#define  CMD_MODE_DATA_WIDTH_MASK			(7 << 13)

#define  CMD_MODE_NOT_SUPPORTED				(0 << 13)

#define  CMD_MODE_DATA_WIDTH_16_BIT			(1 << 13)
@@ -6786,93 +6789,93 @@ enum punit_power_well { 
#define  DATA_LANES_PRG_REG_MASK			(7 << 0)



#define _MIPIA_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb010)

#define _MIPIB_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb810)

#define MIPI_HS_TX_TIMEOUT(tc)	_TRANSCODER(tc, _MIPIA_HS_TX_TIMEOUT, \

					_MIPIB_HS_TX_TIMEOUT)

#define _MIPIC_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb810)

#define MIPI_HS_TX_TIMEOUT(port)	_MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \

					_MIPIC_HS_TX_TIMEOUT)

#define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK		0xffffff



#define _MIPIA_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb014)

#define _MIPIB_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb814)

#define MIPI_LP_RX_TIMEOUT(tc)	_TRANSCODER(tc, _MIPIA_LP_RX_TIMEOUT, \

					_MIPIB_LP_RX_TIMEOUT)

#define _MIPIC_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb814)

#define MIPI_LP_RX_TIMEOUT(port)	_MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \

					_MIPIC_LP_RX_TIMEOUT)

#define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK		0xffffff



#define _MIPIA_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb018)

#define _MIPIB_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb818)

#define MIPI_TURN_AROUND_TIMEOUT(tc)	_TRANSCODER(tc, \

			_MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT)

#define _MIPIC_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb818)

#define MIPI_TURN_AROUND_TIMEOUT(port)	_MIPI_PORT(port, \

			_MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)

#define  TURN_AROUND_TIMEOUT_MASK			0x3f



#define _MIPIA_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb01c)

#define _MIPIB_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb81c)

#define MIPI_DEVICE_RESET_TIMER(tc)	_TRANSCODER(tc, \

			_MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER)

#define _MIPIC_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb81c)

#define MIPI_DEVICE_RESET_TIMER(port)	_MIPI_PORT(port, \

			_MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)

#define  DEVICE_RESET_TIMER_MASK			0xffff



#define _MIPIA_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb020)

#define _MIPIB_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb820)

#define MIPI_DPI_RESOLUTION(tc)	_TRANSCODER(tc, _MIPIA_DPI_RESOLUTION, \

					_MIPIB_DPI_RESOLUTION)

#define _MIPIC_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb820)

#define MIPI_DPI_RESOLUTION(port)	_MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \

					_MIPIC_DPI_RESOLUTION)

#define  VERTICAL_ADDRESS_SHIFT				16

#define  VERTICAL_ADDRESS_MASK				(0xffff << 16)

#define  HORIZONTAL_ADDRESS_SHIFT			0

#define  HORIZONTAL_ADDRESS_MASK			0xffff



#define _MIPIA_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb024)

#define _MIPIB_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb824)

#define MIPI_DBI_FIFO_THROTTLE(tc)	_TRANSCODER(tc, \

			_MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE)

#define _MIPIC_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb824)

#define MIPI_DBI_FIFO_THROTTLE(port)	_MIPI_PORT(port, \

			_MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)

#define  DBI_FIFO_EMPTY_HALF				(0 << 0)

#define  DBI_FIFO_EMPTY_QUARTER				(1 << 0)

#define  DBI_FIFO_EMPTY_7_LOCATIONS			(2 << 0)



/* regs below are bits 15:0 */

#define _MIPIA_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb028)

#define _MIPIB_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb828)

#define MIPI_HSYNC_PADDING_COUNT(tc)	_TRANSCODER(tc, \

			_MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT)

#define _MIPIC_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb828)

#define MIPI_HSYNC_PADDING_COUNT(port)	_MIPI_PORT(port, \

			_MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)



#define _MIPIA_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb02c)

#define _MIPIB_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb82c)

#define MIPI_HBP_COUNT(tc)		_TRANSCODER(tc, _MIPIA_HBP_COUNT, \

					_MIPIB_HBP_COUNT)

#define _MIPIC_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb82c)

#define MIPI_HBP_COUNT(port)		_MIPI_PORT(port, _MIPIA_HBP_COUNT, \

					_MIPIC_HBP_COUNT)



#define _MIPIA_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb030)

#define _MIPIB_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb830)

#define MIPI_HFP_COUNT(tc)		_TRANSCODER(tc, _MIPIA_HFP_COUNT, \

					_MIPIB_HFP_COUNT)

#define _MIPIC_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb830)

#define MIPI_HFP_COUNT(port)		_MIPI_PORT(port, _MIPIA_HFP_COUNT, \

					_MIPIC_HFP_COUNT)



#define _MIPIA_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb034)

#define _MIPIB_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb834)

#define MIPI_HACTIVE_AREA_COUNT(tc)	_TRANSCODER(tc, \

			_MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT)

#define _MIPIC_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb834)

#define MIPI_HACTIVE_AREA_COUNT(port)	_MIPI_PORT(port, \

			_MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)



#define _MIPIA_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb038)

#define _MIPIB_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb838)

#define MIPI_VSYNC_PADDING_COUNT(tc)	_TRANSCODER(tc, \

			_MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT)

#define _MIPIC_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb838)

#define MIPI_VSYNC_PADDING_COUNT(port)	_MIPI_PORT(port, \

			_MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)



#define _MIPIA_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb03c)

#define _MIPIB_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb83c)

#define MIPI_VBP_COUNT(tc)		_TRANSCODER(tc, _MIPIA_VBP_COUNT, \

					_MIPIB_VBP_COUNT)

#define _MIPIC_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb83c)

#define MIPI_VBP_COUNT(port)		_MIPI_PORT(port, _MIPIA_VBP_COUNT, \

					_MIPIC_VBP_COUNT)



#define _MIPIA_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb040)

#define _MIPIB_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb840)

#define MIPI_VFP_COUNT(tc)		_TRANSCODER(tc, _MIPIA_VFP_COUNT, \

					_MIPIB_VFP_COUNT)

#define _MIPIC_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb840)

#define MIPI_VFP_COUNT(port)		_MIPI_PORT(port, _MIPIA_VFP_COUNT, \

					_MIPIC_VFP_COUNT)



#define _MIPIA_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb044)

#define _MIPIB_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb844)

#define MIPI_HIGH_LOW_SWITCH_COUNT(tc)	_TRANSCODER(tc,	\

		_MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT)

#define _MIPIC_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb844)

#define MIPI_HIGH_LOW_SWITCH_COUNT(port)	_MIPI_PORT(port,	\

		_MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)



/* regs above are bits 15:0 */



#define _MIPIA_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb048)

#define _MIPIB_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb848)

#define MIPI_DPI_CONTROL(tc)		_TRANSCODER(tc, _MIPIA_DPI_CONTROL, \

					_MIPIB_DPI_CONTROL)

#define _MIPIC_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb848)

#define MIPI_DPI_CONTROL(port)		_MIPI_PORT(port, _MIPIA_DPI_CONTROL, \

					_MIPIC_DPI_CONTROL)

#define  DPI_LP_MODE					(1 << 6)

#define  BACKLIGHT_OFF					(1 << 5)

#define  BACKLIGHT_ON					(1 << 4)
@@ -6882,30 +6885,30 @@ enum punit_power_well { 
#define  SHUTDOWN					(1 << 0)



#define _MIPIA_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb04c)

#define _MIPIB_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb84c)

#define MIPI_DPI_DATA(tc)		_TRANSCODER(tc, _MIPIA_DPI_DATA, \

					_MIPIB_DPI_DATA)

#define _MIPIC_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb84c)

#define MIPI_DPI_DATA(port)		_MIPI_PORT(port, _MIPIA_DPI_DATA, \

					_MIPIC_DPI_DATA)

#define  COMMAND_BYTE_SHIFT				0

#define  COMMAND_BYTE_MASK				(0x3f << 0)



#define _MIPIA_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb050)

#define _MIPIB_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb850)

#define MIPI_INIT_COUNT(tc)		_TRANSCODER(tc, _MIPIA_INIT_COUNT, \

					_MIPIB_INIT_COUNT)

#define _MIPIC_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb850)

#define MIPI_INIT_COUNT(port)		_MIPI_PORT(port, _MIPIA_INIT_COUNT, \

					_MIPIC_INIT_COUNT)

#define  MASTER_INIT_TIMER_SHIFT			0

#define  MASTER_INIT_TIMER_MASK				(0xffff << 0)



#define _MIPIA_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb054)

#define _MIPIB_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb854)

#define MIPI_MAX_RETURN_PKT_SIZE(tc)	_TRANSCODER(tc, \

			_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE)

#define _MIPIC_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb854)

#define MIPI_MAX_RETURN_PKT_SIZE(port)	_MIPI_PORT(port, \

			_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)

#define  MAX_RETURN_PKT_SIZE_SHIFT			0

#define  MAX_RETURN_PKT_SIZE_MASK			(0x3ff << 0)



#define _MIPIA_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb058)

#define _MIPIB_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb858)

#define MIPI_VIDEO_MODE_FORMAT(tc)	_TRANSCODER(tc, \

			_MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT)

#define _MIPIC_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb858)

#define MIPI_VIDEO_MODE_FORMAT(port)	_MIPI_PORT(port, \

			_MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)

#define  RANDOM_DPI_DISPLAY_RESOLUTION			(1 << 4)

#define  DISABLE_VIDEO_BTA				(1 << 3)

#define  IP_TG_CONFIG					(1 << 2)
@@ -6914,9 +6917,9 @@ enum punit_power_well { 
#define  VIDEO_MODE_BURST				(3 << 0)



#define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)

#define _MIPIB_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)

#define MIPI_EOT_DISABLE(tc)		_TRANSCODER(tc, _MIPIA_EOT_DISABLE, \

					_MIPIB_EOT_DISABLE)

#define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)

#define MIPI_EOT_DISABLE(port)		_MIPI_PORT(port, _MIPIA_EOT_DISABLE, \

					_MIPIC_EOT_DISABLE)

#define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 7)

#define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 6)

#define  LOW_CONTENTION_RECOVERY_DISABLE		(1 << 5)
@@ -6927,32 +6930,32 @@ enum punit_power_well { 
#define  EOT_DISABLE					(1 << 0)



#define _MIPIA_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb060)

#define _MIPIB_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb860)

#define MIPI_LP_BYTECLK(tc)		_TRANSCODER(tc, _MIPIA_LP_BYTECLK, \

					_MIPIB_LP_BYTECLK)

#define _MIPIC_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb860)

#define MIPI_LP_BYTECLK(port)		_MIPI_PORT(port, _MIPIA_LP_BYTECLK, \

					_MIPIC_LP_BYTECLK)

#define  LP_BYTECLK_SHIFT				0

#define  LP_BYTECLK_MASK				(0xffff << 0)



/* bits 31:0 */

#define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)

#define _MIPIB_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)

#define MIPI_LP_GEN_DATA(tc)		_TRANSCODER(tc, _MIPIA_LP_GEN_DATA, \

					_MIPIB_LP_GEN_DATA)

#define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)

#define MIPI_LP_GEN_DATA(port)		_MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \

					_MIPIC_LP_GEN_DATA)



/* bits 31:0 */

#define _MIPIA_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb068)

#define _MIPIB_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb868)

#define MIPI_HS_GEN_DATA(tc)		_TRANSCODER(tc, _MIPIA_HS_GEN_DATA, \

					_MIPIB_HS_GEN_DATA)

#define _MIPIC_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb868)

#define MIPI_HS_GEN_DATA(port)		_MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \

					_MIPIC_HS_GEN_DATA)



#define _MIPIA_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb06c)

#define _MIPIB_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb86c)

#define MIPI_LP_GEN_CTRL(tc)		_TRANSCODER(tc, _MIPIA_LP_GEN_CTRL, \

					_MIPIB_LP_GEN_CTRL)

#define _MIPIC_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb86c)

#define MIPI_LP_GEN_CTRL(port)		_MIPI_PORT(port, _MIPIA_LP_GEN_CTRL, \

					_MIPIC_LP_GEN_CTRL)

#define _MIPIA_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb070)

#define _MIPIB_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb870)

#define MIPI_HS_GEN_CTRL(tc)		_TRANSCODER(tc, _MIPIA_HS_GEN_CTRL, \

					_MIPIB_HS_GEN_CTRL)

#define _MIPIC_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb870)

#define MIPI_HS_GEN_CTRL(port)		_MIPI_PORT(port, _MIPIA_HS_GEN_CTRL, \

					_MIPIC_HS_GEN_CTRL)

#define  LONG_PACKET_WORD_COUNT_SHIFT			8

#define  LONG_PACKET_WORD_COUNT_MASK			(0xffff << 8)

#define  SHORT_PACKET_PARAM_SHIFT			8
@@ -6964,9 +6967,9 @@ enum punit_power_well { 
/* data type values, see include/video/mipi_display.h */



#define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)

#define _MIPIB_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb874)

#define MIPI_GEN_FIFO_STAT(tc)	_TRANSCODER(tc, _MIPIA_GEN_FIFO_STAT, \

					_MIPIB_GEN_FIFO_STAT)

#define _MIPIC_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb874)

#define MIPI_GEN_FIFO_STAT(port)	_MIPI_PORT(port, _MIPIA_GEN_FIFO_STAT, \

					_MIPIC_GEN_FIFO_STAT)

#define  DPI_FIFO_EMPTY					(1 << 28)

#define  DBI_FIFO_EMPTY					(1 << 27)

#define  LP_CTRL_FIFO_EMPTY				(1 << 26)
@@ -6983,17 +6986,17 @@ enum punit_power_well { 
#define  HS_DATA_FIFO_FULL				(1 << 0)



#define _MIPIA_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb078)

#define _MIPIB_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb878)

#define MIPI_HS_LP_DBI_ENABLE(tc)	_TRANSCODER(tc, \

			_MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE)

#define _MIPIC_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb878)

#define MIPI_HS_LP_DBI_ENABLE(port)	_MIPI_PORT(port, \

			_MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)

#define  DBI_HS_LP_MODE_MASK				(1 << 0)

#define  DBI_LP_MODE					(1 << 0)

#define  DBI_HS_MODE					(0 << 0)



#define _MIPIA_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb080)

#define _MIPIB_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb880)

#define MIPI_DPHY_PARAM(tc)		_TRANSCODER(tc, _MIPIA_DPHY_PARAM, \

					_MIPIB_DPHY_PARAM)

#define _MIPIC_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb880)

#define MIPI_DPHY_PARAM(port)		_MIPI_PORT(port, _MIPIA_DPHY_PARAM, \

					_MIPIC_DPHY_PARAM)

#define  EXIT_ZERO_COUNT_SHIFT				24

#define  EXIT_ZERO_COUNT_MASK				(0x3f << 24)

#define  TRAIL_COUNT_SHIFT				16
@@ -7005,36 +7008,36 @@ enum punit_power_well { 


/* bits 31:0 */

#define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)

#define _MIPIB_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)

#define MIPI_DBI_BW_CTRL(tc)		_TRANSCODER(tc, _MIPIA_DBI_BW_CTRL, \

					_MIPIB_DBI_BW_CTRL)

#define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)

#define MIPI_DBI_BW_CTRL(port)		_MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \

					_MIPIC_DBI_BW_CTRL)



#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base \

							+ 0xb088)

#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base \

#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base \

							+ 0xb888)

#define MIPI_CLK_LANE_SWITCH_TIME_CNT(tc)	_TRANSCODER(tc, \

	_MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT)

#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)	_MIPI_PORT(port, \

	_MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)

#define  LP_HS_SSW_CNT_SHIFT				16

#define  LP_HS_SSW_CNT_MASK				(0xffff << 16)

#define  HS_LP_PWR_SW_CNT_SHIFT				0

#define  HS_LP_PWR_SW_CNT_MASK				(0xffff << 0)



#define _MIPIA_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb08c)

#define _MIPIB_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb88c)

#define MIPI_STOP_STATE_STALL(tc)	_TRANSCODER(tc, \

			_MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL)

#define _MIPIC_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb88c)

#define MIPI_STOP_STATE_STALL(port)	_MIPI_PORT(port, \

			_MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)

#define  STOP_STATE_STALL_COUNTER_SHIFT			0

#define  STOP_STATE_STALL_COUNTER_MASK			(0xff << 0)



#define _MIPIA_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb090)

#define _MIPIB_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb890)

#define MIPI_INTR_STAT_REG_1(tc)	_TRANSCODER(tc, \

				_MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1)

#define _MIPIC_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb890)

#define MIPI_INTR_STAT_REG_1(port)	_MIPI_PORT(port, \

				_MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)

#define _MIPIA_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb094)

#define _MIPIB_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb894)

#define MIPI_INTR_EN_REG_1(tc)	_TRANSCODER(tc, _MIPIA_INTR_EN_REG_1, \

					_MIPIB_INTR_EN_REG_1)

#define _MIPIC_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb894)

#define MIPI_INTR_EN_REG_1(port)	_MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \

					_MIPIC_INTR_EN_REG_1)

#define  RX_CONTENTION_DETECTED				(1 << 0)



/* XXX: only pipe A ?!? */
@@ -7053,9 +7056,9 @@ enum punit_power_well { 
/* MIPI adapter registers */



#define _MIPIA_CTRL			(dev_priv->mipi_mmio_base + 0xb104)

#define _MIPIB_CTRL			(dev_priv->mipi_mmio_base + 0xb904)

#define MIPI_CTRL(tc)			_TRANSCODER(tc, _MIPIA_CTRL, \

					_MIPIB_CTRL)

#define _MIPIC_CTRL			(dev_priv->mipi_mmio_base + 0xb904)

#define MIPI_CTRL(port)			_MIPI_PORT(port, _MIPIA_CTRL, \

					_MIPIC_CTRL)

#define  ESCAPE_CLOCK_DIVIDER_SHIFT			5 /* A only */

#define  ESCAPE_CLOCK_DIVIDER_MASK			(3 << 5)

#define  ESCAPE_CLOCK_DIVIDER_1				(0 << 5)
@@ -7068,24 +7071,24 @@ enum punit_power_well { 
#define  RGB_FLIP_TO_BGR				(1 << 2)



#define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)

#define _MIPIB_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)

#define MIPI_DATA_ADDRESS(tc)		_TRANSCODER(tc, _MIPIA_DATA_ADDRESS, \

					_MIPIB_DATA_ADDRESS)

#define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)

#define MIPI_DATA_ADDRESS(port)		_MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \

					_MIPIC_DATA_ADDRESS)

#define  DATA_MEM_ADDRESS_SHIFT				5

#define  DATA_MEM_ADDRESS_MASK				(0x7ffffff << 5)

#define  DATA_VALID					(1 << 0)



#define _MIPIA_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb10c)

#define _MIPIB_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb90c)

#define MIPI_DATA_LENGTH(tc)		_TRANSCODER(tc, _MIPIA_DATA_LENGTH, \

					_MIPIB_DATA_LENGTH)

#define _MIPIC_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb90c)

#define MIPI_DATA_LENGTH(port)		_MIPI_PORT(port, _MIPIA_DATA_LENGTH, \

					_MIPIC_DATA_LENGTH)

#define  DATA_LENGTH_SHIFT				0

#define  DATA_LENGTH_MASK				(0xfffff << 0)



#define _MIPIA_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb110)

#define _MIPIB_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb910)

#define MIPI_COMMAND_ADDRESS(tc)	_TRANSCODER(tc, \

				_MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS)

#define _MIPIC_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb910)

#define MIPI_COMMAND_ADDRESS(port)	_MIPI_PORT(port, \

				_MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)

#define  COMMAND_MEM_ADDRESS_SHIFT			5

#define  COMMAND_MEM_ADDRESS_MASK			(0x7ffffff << 5)

#define  AUTO_PWG_ENABLE				(1 << 2)
@@ -7093,22 +7096,22 @@ enum punit_power_well { 
#define  COMMAND_VALID					(1 << 0)



#define _MIPIA_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb114)

#define _MIPIB_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb914)

#define MIPI_COMMAND_LENGTH(tc)	_TRANSCODER(tc, _MIPIA_COMMAND_LENGTH, \

					_MIPIB_COMMAND_LENGTH)

#define _MIPIC_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb914)

#define MIPI_COMMAND_LENGTH(port)	_MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \

					_MIPIC_COMMAND_LENGTH)

#define  COMMAND_LENGTH_SHIFT(n)			(8 * (n)) /* n: 0...3 */

#define  COMMAND_LENGTH_MASK(n)				(0xff << (8 * (n)))



#define _MIPIA_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb118)

#define _MIPIB_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb918)

#define MIPI_READ_DATA_RETURN(tc, n) \

	(_TRANSCODER(tc, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) \

#define _MIPIC_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb918)

#define MIPI_READ_DATA_RETURN(port, n) \

	(_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \

					+ 4 * (n)) /* n: 0...7 */



#define _MIPIA_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb138)

#define _MIPIB_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb938)

#define MIPI_READ_DATA_VALID(tc)	_TRANSCODER(tc, \

				_MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)

#define _MIPIC_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb938)

#define MIPI_READ_DATA_VALID(port)	_MIPI_PORT(port, \

				_MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)

#define  READ_DATA_VALID(n)				(1 << (n))



/* For UMS only (deprecated): */

drivers/gpu/drm/i915/intel_dsi.c

+76 −72

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/i915/intel_dsi.h

+16 −0
Original line number Diff line number Diff line
@@ -127,6 +127,22 @@ struct intel_dsi { 
	u16 panel_pwr_cycle_delay;

};



/* XXX: Transitional before dual port configuration */

static inline enum port intel_dsi_pipe_to_port(enum pipe pipe)

{

	if (pipe == PIPE_A)

		return PORT_A;

	else if (pipe == PIPE_B)

		return PORT_C;



	WARN(1, "DSI on pipe %c, assuming port C\n", pipe_name(pipe));

	return PORT_C;

}



#define for_each_dsi_port(__port, __ports_mask) \

	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\

		if ((__ports_mask) & (1 << (__port)))



static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)

{

	return container_of(encoder, struct intel_dsi, base.base);

drivers/gpu/drm/i915/intel_dsi_cmd.c

+32 −32

File changed.

Preview size limit exceeded, changes collapsed.