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Commit e6292556 authored by Vandana Kannan's avatar Vandana Kannan Committed by Daniel Vetter
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drm/i915/bxt: BUNs related to port PLL 



This patch contains changes based on 2 updates to the spec:
Port PLL VCO restriction raised up to 6700.
Port PLL now needs DCO amp override enable for all VCO frequencies.

v2: Sonika's review comment addressed
	- dcoampovr_en_h variable not required
Based on a discussion with Siva, the following changes have been made.
	- replace dco_amp var with #define BXT_DCO_AMPLITUDE
	- set pll10 in a single assignment

v3:
Move DCO amplitude default value to i915_reg.h. Suggested by Siva.

Signed-off-by: default avatarVandana Kannan <vandana.kannan@intel.com>
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> [v2]
[danvet: Spell out BUN since not everyone knows what this means.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 7a0baa62

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -1215,6 +1215,7 @@ enum skl_disp_power_wells { 
#define  PORT_PLL_LOCK_THRESHOLD_MASK	(0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)

/* PORT_PLL_10_A */

#define  PORT_PLL_DCO_AMP_OVR_EN_H	(1<<27)

#define  PORT_PLL_DCO_AMP_DEFAULT	15

#define  PORT_PLL_DCO_AMP_MASK		0x3c00

#define  PORT_PLL_DCO_AMP(x)		(x<<10)

#define _PORT_PLL_BASE(port)		_PORT3(port, _PORT_PLL_0_A,	\

drivers/gpu/drm/i915/intel_ddi.c

+5 −10
Original line number Diff line number Diff line
@@ -1644,7 +1644,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, 
	struct bxt_clk_div clk_div = {0};

	int vco = 0;

	uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;

	uint32_t dcoampovr_en_h, dco_amp, lanestagger;

	uint32_t lanestagger;



	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {

		intel_clock_t best_clock;
@@ -1683,9 +1683,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, 
		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;

	}



	dco_amp = 15;

	dcoampovr_en_h = 0;

	if (vco >= 6200000 && vco <= 6480000) {

	if (vco >= 6200000 && vco <= 6700000) {

		prop_coef = 4;

		int_coef = 9;

		gain_ctl = 3;
@@ -1696,8 +1694,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, 
		int_coef = 11;

		gain_ctl = 3;

		targ_cnt = 9;

		if (vco >= 4800000 && vco < 5400000)

			dcoampovr_en_h = 1;

	} else if (vco == 5400000) {

		prop_coef = 3;

		int_coef = 8;
@@ -1741,10 +1737,9 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, 


	crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;



	if (dcoampovr_en_h)

		crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;



	crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);

	crtc_state->dpll_hw_state.pll10 =

		PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)

		| PORT_PLL_DCO_AMP_OVR_EN_H;



	crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;

drivers/gpu/drm/i915/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -409,7 +409,7 @@ static const intel_limit_t intel_limits_chv = { 
static const intel_limit_t intel_limits_bxt = {

	/* FIXME: find real dot limits */

	.dot = { .min = 0, .max = INT_MAX },

	.vco = { .min = 4800000, .max = 6480000 },

	.vco = { .min = 4800000, .max = 6700000 },

	.n = { .min = 1, .max = 1 },

	.m1 = { .min = 2, .max = 2 },

	/* FIXME: find real m2 limits */