Merge git://github.com/Jkirsher/net-next (e3b37a1b) · Commits · e / devices / android_kernel_samsung_universal8895

drivers/net/ethernet/intel/ixgbe/ixgbe.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -53,6 +53,7 @@

	/* TX/RX descriptor defines */		/* TX/RX descriptor defines */
	#define IXGBE_DEFAULT_TXD 512		#define IXGBE_DEFAULT_TXD 512
			#define IXGBE_DEFAULT_TX_WORK 256
	#define IXGBE_MAX_TXD 4096		#define IXGBE_MAX_TXD 4096
	#define IXGBE_MIN_TXD 64		#define IXGBE_MIN_TXD 64

	@@ -490,7 +491,6 @@ struct ixgbe_adapter {
	int node;		int node;
	u32 led_reg;		u32 led_reg;
	u32 interrupt_event;		u32 interrupt_event;
	char lsc_int_name[IFNAMSIZ + 9];

	/* SR-IOV */		/* SR-IOV */
	DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);		DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);

drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c

+5 −8

Original line number	Original line	Diff line number	Diff line
	@@ -820,8 +820,8 @@ mac_reset_top:
	* Issue global reset to the MAC. This needs to be a SW reset.		* Issue global reset to the MAC. This needs to be a SW reset.
	* If link reset is used, it might reset the MAC when mng is using it		* If link reset is used, it might reset the MAC when mng is using it
	*/		*/
	ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) \| IXGBE_CTRL_RST;
	IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl \| IXGBE_CTRL_RST));		IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
	IXGBE_WRITE_FLUSH(hw);		IXGBE_WRITE_FLUSH(hw);

	/* Poll for reset bit to self-clear indicating reset is complete */		/* Poll for reset bit to self-clear indicating reset is complete */
	@@ -836,21 +836,18 @@ mac_reset_top:
	hw_dbg(hw, "Reset polling failed to complete.\n");		hw_dbg(hw, "Reset polling failed to complete.\n");
	}		}

			msleep(50);

	/*		/*
	* Double resets are required for recovery from certain error		* Double resets are required for recovery from certain error
	* conditions. Between resets, it is necessary to stall to allow time		* conditions. Between resets, it is necessary to stall to allow time
	* for any pending HW events to complete. We use 1usec since that is		* for any pending HW events to complete.
	* what is needed for ixgbe_disable_pcie_master(). The second reset
	* then clears out any effects of those events.
	*/		*/
	if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {		if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
	hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;		hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
	udelay(1);
	goto mac_reset_top;		goto mac_reset_top;
	}		}

	msleep(50);

	gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);		gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
	gheccr &= ~((1 << 21) \| (1 << 18) \| (1 << 9) \| (1 << 6));		gheccr &= ~((1 << 21) \| (1 << 18) \| (1 << 9) \| (1 << 6));
	IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);		IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);

drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c

+23 −17

Original line number	Original line	Diff line number	Diff line
	@@ -904,11 +904,10 @@ static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
	**/		**/
	static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)		static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
	{		{
	s32 status = 0;		ixgbe_link_speed link_speed;
	u32 ctrl;		s32 status;
	u32 i;		u32 ctrl, i, autoc, autoc2;
	u32 autoc;		bool link_up = false;
	u32 autoc2;

	/* Call adapter stop to disable tx/rx and clear interrupts */		/* Call adapter stop to disable tx/rx and clear interrupts */
	hw->mac.ops.stop_adapter(hw);		hw->mac.ops.stop_adapter(hw);
	@@ -942,40 +941,47 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)

	mac_reset_top:		mac_reset_top:
	/*		/*
	* Issue global reset to the MAC. This needs to be a SW reset.		* Issue global reset to the MAC. Needs to be SW reset if link is up.
	* If link reset is used, it might reset the MAC when mng is using it		* If link reset is used when link is up, it might reset the PHY when
			* mng is using it. If link is down or the flag to force full link
			* reset is set, then perform link reset.
	*/		*/
	ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);		ctrl = IXGBE_CTRL_LNK_RST;
	IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl \| IXGBE_CTRL_RST));		if (!hw->force_full_reset) {
			hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
			if (link_up)
			ctrl = IXGBE_CTRL_RST;
			}

			ctrl \|= IXGBE_READ_REG(hw, IXGBE_CTRL);
			IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
	IXGBE_WRITE_FLUSH(hw);		IXGBE_WRITE_FLUSH(hw);

	/* Poll for reset bit to self-clear indicating reset is complete */		/* Poll for reset bit to self-clear indicating reset is complete */
	for (i = 0; i < 10; i++) {		for (i = 0; i < 10; i++) {
	udelay(1);		udelay(1);
	ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
	if (!(ctrl & IXGBE_CTRL_RST))		if (!(ctrl & IXGBE_CTRL_RST_MASK))
	break;		break;
	}		}
	if (ctrl & IXGBE_CTRL_RST) {
			if (ctrl & IXGBE_CTRL_RST_MASK) {
	status = IXGBE_ERR_RESET_FAILED;		status = IXGBE_ERR_RESET_FAILED;
	hw_dbg(hw, "Reset polling failed to complete.\n");		hw_dbg(hw, "Reset polling failed to complete.\n");
	}		}

			msleep(50);

	/*		/*
	* Double resets are required for recovery from certain error		* Double resets are required for recovery from certain error
	* conditions. Between resets, it is necessary to stall to allow time		* conditions. Between resets, it is necessary to stall to allow time
	* for any pending HW events to complete. We use 1usec since that is		* for any pending HW events to complete.
	* what is needed for ixgbe_disable_pcie_master(). The second reset
	* then clears out any effects of those events.
	*/		*/
	if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {		if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
	hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;		hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
	udelay(1);
	goto mac_reset_top;		goto mac_reset_top;
	}		}

	msleep(50);

	/*		/*
	* Store the original AUTOC/AUTOC2 values if they have not been		* Store the original AUTOC/AUTOC2 values if they have not been
	* stored off yet. Otherwise restore the stored original		* stored off yet. Otherwise restore the stored original

drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c

+9 −9

Original line number	Original line	Diff line number	Diff line
	@@ -1570,26 +1570,26 @@ static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)

	/* X540 needs to set the MACC.FLU bit to force link up */		/* X540 needs to set the MACC.FLU bit to force link up */
	if (adapter->hw.mac.type == ixgbe_mac_X540) {		if (adapter->hw.mac.type == ixgbe_mac_X540) {
	reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MACC);		reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
	reg_data \|= IXGBE_MACC_FLU;		reg_data \|= IXGBE_MACC_FLU;
	IXGBE_WRITE_REG(&adapter->hw, IXGBE_MACC, reg_data);		IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
	}		}

	/* right now we only support MAC loopback in the driver */		/* right now we only support MAC loopback in the driver */
	reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);		reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
	/* Setup MAC loopback */		/* Setup MAC loopback */
	reg_data \|= IXGBE_HLREG0_LPBK;		reg_data \|= IXGBE_HLREG0_LPBK;
	IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);		IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);

	reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);		reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
	reg_data \|= IXGBE_FCTRL_BAM \| IXGBE_FCTRL_SBP \| IXGBE_FCTRL_MPE;		reg_data \|= IXGBE_FCTRL_BAM \| IXGBE_FCTRL_SBP \| IXGBE_FCTRL_MPE;
	IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);		IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);

	reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);		reg_data = IXGBE_READ_REG(hw, IXGBE_AUTOC);
	reg_data &= ~IXGBE_AUTOC_LMS_MASK;		reg_data &= ~IXGBE_AUTOC_LMS_MASK;
	reg_data \|= IXGBE_AUTOC_LMS_10G_LINK_NO_AN \| IXGBE_AUTOC_FLU;		reg_data \|= IXGBE_AUTOC_LMS_10G_LINK_NO_AN \| IXGBE_AUTOC_FLU;
	IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
	IXGBE_WRITE_FLUSH(&adapter->hw);		IXGBE_WRITE_FLUSH(hw);
	usleep_range(10000, 20000);		usleep_range(10000, 20000);

	/* Disable Atlas Tx lanes; re-enabled in reset path */		/* Disable Atlas Tx lanes; re-enabled in reset path */

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

+288 −487

File changed.

Preview size limit exceeded, changes collapsed.