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Commit e1c171b8 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/jiang-pcie-cap' into next 

* pci/jiang-pcie-cap: (40 commits)
  rtl8192e: Use PCI Express Capability accessors
  et131x: Use PCI Express Capability accessors
  rapdio/tsi721: Use PCI Express Capability accessors
  drm/radeon: Use PCI Express Capability accessors
  [SCSI] qla4xxx: Use PCI Express Capability accessors
  [SCSI] qla4xxx: Use PCI Express Capability accessors
  IB/qib: Use PCI Express Capability accessors
  IB/mthca: Use PCI Express Capability accessors
  rtlwifi: Use PCI Express Capability accessors
  iwlwifi: Use PCI Express Capability accessors
  iwlegacy: Use PCI Express Capability accessors
  ath9k: Use PCI Express Capability accessors
  atl1c: Use PCI Express Capability accessors
  cxgb4: Use PCI Express Capability accessors
  cxgb3: Use PCI Express Capability accessors
  myri10ge: Use PCI Express Capability accessors
  niu: Use PCI Express Capability accessors
  mlx4: Use PCI Express Capability accessors
  vxge: Use PCI Express Capability accessors
  igb: Use PCI Express Capability accessors
  ...
parents 0d7614f0 479e0d48

arch/arm/mach-tegra/pcie.c

+1 −11
Original line number Diff line number Diff line
@@ -367,17 +367,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class); 
/* Tegra PCIE requires relaxed ordering */

static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev)

{

	u16 val16;

	int pos = pci_find_capability(dev, PCI_CAP_ID_EXP);



	if (pos <= 0) {

		dev_err(&dev->dev, "skipping relaxed ordering fixup\n");

		return;

	}



	pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16);

	val16 |= PCI_EXP_DEVCTL_RELAX_EN;

	pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16);

	pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);

}

DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);

arch/mips/pci/pci-octeon.c

+5 −10
Original line number Diff line number Diff line
@@ -117,16 +117,11 @@ int pcibios_plat_dev_init(struct pci_dev *dev) 
	}



	/* Enable the PCIe normal error reporting */

	pos = pci_find_capability(dev, PCI_CAP_ID_EXP);

	if (pos) {

		/* Update Device Control */

		pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);

		config |= PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */

	config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */

	config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */

	config |= PCI_EXP_DEVCTL_FERE;  /* Fatal Error Reporting */

	config |= PCI_EXP_DEVCTL_URRE;  /* Unsupported Request */

		pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);

	}

	pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);



	/* Find the Advanced Error Reporting capability */

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);

arch/powerpc/platforms/powernv/pci-ioda.c

+1 −1
Original line number Diff line number Diff line
@@ -855,7 +855,7 @@ static void __devinit pnv_ioda_setup_PEs(struct pci_bus *bus) 
		if (pe == NULL)

			continue;

		/* Leaving the PCIe domain ... single PE# */

		if (dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)

		if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)

			pnv_ioda_setup_bus_PE(dev, pe);

		else if (dev->subordinate)

			pnv_ioda_setup_PEs(dev->subordinate);

arch/tile/kernel/pci.c

+6 −20
Original line number Diff line number Diff line
@@ -246,16 +246,13 @@ static void __devinit fixup_read_and_payload_sizes(void) 


	/* Scan for the smallest maximum payload size. */

	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {

		int pcie_caps_offset;

		u32 devcap;

		int max_payload;



		pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);

		if (pcie_caps_offset == 0)

		if (!pci_is_pcie(dev))

			continue;



		pci_read_config_dword(dev, pcie_caps_offset + PCI_EXP_DEVCAP,

				      &devcap);

		pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &devcap);

		max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD;

		if (max_payload < smallest_max_payload)

			smallest_max_payload = max_payload;
@@ -263,21 +260,10 @@ static void __devinit fixup_read_and_payload_sizes(void) 


	/* Now, set the max_payload_size for all devices to that value. */

	new_values = (max_read_size << 12) | (smallest_max_payload << 5);

	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {

		int pcie_caps_offset;

		u16 devctl;



		pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);

		if (pcie_caps_offset == 0)

			continue;



		pci_read_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,

				     &devctl);

		devctl &= ~(PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ);

		devctl |= new_values;

		pci_write_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,

				      devctl);

	}

	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)

		pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,

				PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ,

				new_values);

}

drivers/gpu/drm/radeon/evergreen.c

+3 −7
Original line number Diff line number Diff line
@@ -77,13 +77,9 @@ void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 
void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)

{

	u16 ctl, v;

	int cap, err;

	int err;



	cap = pci_pcie_cap(rdev->pdev);

	if (!cap)

		return;



	err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);

	err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);

	if (err)

		return;
@@ -95,7 +91,7 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) 
	if ((v == 0) || (v == 6) || (v == 7)) {

		ctl &= ~PCI_EXP_DEVCTL_READRQ;

		ctl |= (2 << 12);

		pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);

		pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);

	}

}