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Commit dfd07d72 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: clean up PIPECONF bpc #defines 



Ilk+ somehow used #defines in near the PIPESTAT definitions, which
decently confused me. Earlier platforms called it BPP instead of
BPC. Clean this all up.

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f0a3424e

drivers/gpu/drm/i915/i915_reg.h

+5 −10
Original line number Original line Diff line number Diff line
@@ -2648,11 +2648,11 @@ 
#define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */

#define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */

#define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */

#define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */

#define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)

#define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)

#define   PIPECONF_BPP_MASK	(0x000000e0)

#define   PIPECONF_BPC_MASK	(0x7 << 5)

#define   PIPECONF_BPP_8	(0<<5)

#define   PIPECONF_8BPC		(0<<5)

#define   PIPECONF_BPP_10	(1<<5)

#define   PIPECONF_10BPC	(1<<5)

#define   PIPECONF_BPP_6	(2<<5)

#define   PIPECONF_6BPC		(2<<5)

#define   PIPECONF_BPP_12	(3<<5)

#define   PIPECONF_12BPC	(3<<5)

#define   PIPECONF_DITHER_EN	(1<<4)

#define   PIPECONF_DITHER_EN	(1<<4)

#define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)

#define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)

#define   PIPECONF_DITHER_TYPE_SP (0<<2)

#define   PIPECONF_DITHER_TYPE_SP (0<<2)
@@ -2696,11 +2696,6 @@ 
#define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or later */

#define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or later */

#define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)

#define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)

#define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)

#define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)

#define   PIPE_BPC_MASK				(7 << 5) /* Ironlake */

#define   PIPE_8BPC				(0 << 5)

#define   PIPE_10BPC				(1 << 5)

#define   PIPE_6BPC				(2 << 5)

#define   PIPE_12BPC				(3 << 5)





#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)

#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)

#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)

#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)

drivers/gpu/drm/i915/intel_display.c

+14 −14
Original line number Original line Diff line number Diff line
@@ -1669,8 +1669,8 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, 
		 * make the BPC in transcoder be consistent with

		 * make the BPC in transcoder be consistent with

		 * that in pipeconf reg.

		 * that in pipeconf reg.

		 */

		 */

		val &= ~PIPE_BPC_MASK;

		val &= ~PIPECONF_BPC_MASK;

		val |= pipeconf_val & PIPE_BPC_MASK;

		val |= pipeconf_val & PIPECONF_BPC_MASK;

	}

	}





	val &= ~TRANS_INTERLACE_MASK;

	val &= ~TRANS_INTERLACE_MASK;
@@ -2764,7 +2764,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) 
	temp = I915_READ(reg);

	temp = I915_READ(reg);

	temp &= ~((0x7 << 19) | (0x7 << 16));

	temp &= ~((0x7 << 19) | (0x7 << 16));

	temp |= (intel_crtc->fdi_lanes - 1) << 19;

	temp |= (intel_crtc->fdi_lanes - 1) << 19;

	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;

	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;

	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);

	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);





	POSTING_READ(reg);

	POSTING_READ(reg);
@@ -2845,7 +2845,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc) 
	reg = FDI_RX_CTL(pipe);

	reg = FDI_RX_CTL(pipe);

	temp = I915_READ(reg);

	temp = I915_READ(reg);

	temp &= ~(0x7 << 16);

	temp &= ~(0x7 << 16);

	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;

	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;

	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);

	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);





	POSTING_READ(reg);

	POSTING_READ(reg);
@@ -2876,7 +2876,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc) 
	}

	}

	/* BPC in FDI rx is consistent with that in PIPECONF */

	/* BPC in FDI rx is consistent with that in PIPECONF */

	temp &= ~(0x07 << 16);

	temp &= ~(0x07 << 16);

	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;

	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;

	I915_WRITE(reg, temp);

	I915_WRITE(reg, temp);





	POSTING_READ(reg);

	POSTING_READ(reg);
@@ -3115,7 +3115,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) 
	if (HAS_PCH_CPT(dev) &&

	if (HAS_PCH_CPT(dev) &&

	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||

	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||

	     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {

	     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {

		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;

		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;

		reg = TRANS_DP_CTL(pipe);

		reg = TRANS_DP_CTL(pipe);

		temp = I915_READ(reg);

		temp = I915_READ(reg);

		temp &= ~(TRANS_DP_PORT_SEL_MASK |

		temp &= ~(TRANS_DP_PORT_SEL_MASK |
@@ -4686,10 +4686,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 
	}

	}





	/* default to 8bpc */

	/* default to 8bpc */

	pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);

	pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);

	if (is_dp) {

	if (is_dp) {

		if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {

		if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {

			pipeconf |= PIPECONF_BPP_6 |

			pipeconf |= PIPECONF_6BPC |

				    PIPECONF_DITHER_EN |

				    PIPECONF_DITHER_EN |

				    PIPECONF_DITHER_TYPE_SP;

				    PIPECONF_DITHER_TYPE_SP;

		}

		}
@@ -4697,7 +4697,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 




	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {

	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {

		if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {

		if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {

			pipeconf |= PIPECONF_BPP_6 |

			pipeconf |= PIPECONF_6BPC |

					PIPECONF_ENABLE |

					PIPECONF_ENABLE |

					I965_PIPECONF_ACTIVE;

					I965_PIPECONF_ACTIVE;

		}

		}
@@ -4907,19 +4907,19 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc, 




	val = I915_READ(PIPECONF(pipe));

	val = I915_READ(PIPECONF(pipe));





	val &= ~PIPE_BPC_MASK;

	val &= ~PIPECONF_BPC_MASK;

	switch (intel_crtc->bpp) {

	switch (intel_crtc->bpp) {

	case 18:

	case 18:

		val |= PIPE_6BPC;

		val |= PIPECONF_6BPC;

		break;

		break;

	case 24:

	case 24:

		val |= PIPE_8BPC;

		val |= PIPECONF_8BPC;

		break;

		break;

	case 30:

	case 30:

		val |= PIPE_10BPC;

		val |= PIPECONF_10BPC;

		break;

		break;

	case 36:

	case 36:

		val |= PIPE_12BPC;

		val |= PIPECONF_12BPC;

		break;

		break;

	default:

	default:

		/* Case prevented by intel_choose_pipe_bpp_dither. */

		/* Case prevented by intel_choose_pipe_bpp_dither. */