ARM: S3C24XX: remove legacy clock code (defd9da5) · Commits · e / devices / android_kernel_samsung_universal8895

arch/arm/mach-s3c24xx/Kconfig

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	@@ -110,17 +110,6 @@ config CPU_S3C2443

	# common code		# common code

	config S3C2410_CLOCK
	bool
	help
	Clock code for the S3C2410, and similar processors which
	is currently includes the S3C2410, S3C2440, S3C2442.

	config S3C24XX_DCLK
	bool
	help
	Clock code for supporting DCLK/CLKOUT on S3C24XX architectures

	config S3C24XX_SMDK		config S3C24XX_SMDK
	bool		bool
	help		help

arch/arm/mach-s3c24xx/Makefile

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	@@ -44,10 +44,8 @@ obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o

	# common code		# common code

	obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
	obj-$(CONFIG_S3C24XX_DMA) += dma.o		obj-$(CONFIG_S3C24XX_DMA) += dma.o

	obj-$(CONFIG_S3C2410_CLOCK) += clock-s3c2410.o
	obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o		obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o

	obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o		obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o

arch/arm/mach-s3c24xx/clock-dclk.c

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	/*
	* Copyright (c) 2004-2008 Simtec Electronics
	* Ben Dooks <ben@simtec.co.uk>
	* http://armlinux.simtec.co.uk/
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2 as
	* published by the Free Software Foundation.
	*
	* S3C24XX - definitions for DCLK and CLKOUT registers
	*/

	#include <linux/kernel.h>
	#include <linux/errno.h>
	#include <linux/clk.h>
	#include <linux/io.h>

	#include <mach/regs-clock.h>
	#include <mach/regs-gpio.h>

	#include <plat/clock.h>
	#include <plat/cpu.h>

	/* clocks that could be registered by external code */

	static int s3c24xx_dclk_enable(struct clk *clk, int enable)
	{
	unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);

	if (enable)
	dclkcon \|= clk->ctrlbit;
	else
	dclkcon &= ~clk->ctrlbit;

	__raw_writel(dclkcon, S3C24XX_DCLKCON);

	return 0;
	}

	static int s3c24xx_dclk_setparent(struct clk clk, struct clk parent)
	{
	unsigned long dclkcon;
	unsigned int uclk;

	if (parent == &clk_upll)
	uclk = 1;
	else if (parent == &clk_p)
	uclk = 0;
	else
	return -EINVAL;

	clk->parent = parent;

	dclkcon = __raw_readl(S3C24XX_DCLKCON);

	if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
	if (uclk)
	dclkcon \|= S3C2410_DCLKCON_DCLK0_UCLK;
	else
	dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
	} else {
	if (uclk)
	dclkcon \|= S3C2410_DCLKCON_DCLK1_UCLK;
	else
	dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
	}

	__raw_writel(dclkcon, S3C24XX_DCLKCON);

	return 0;
	}
	static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
	{
	unsigned long div;

	if ((rate == 0) \|\| !clk->parent)
	return 0;

	div = clk_get_rate(clk->parent) / rate;
	if (div < 2)
	div = 2;
	else if (div > 16)
	div = 16;

	return div;
	}

	static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
	unsigned long rate)
	{
	unsigned long div = s3c24xx_calc_div(clk, rate);

	if (div == 0)
	return 0;

	return clk_get_rate(clk->parent) / div;
	}

	static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
	{
	unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);

	if (div == 0)
	return -EINVAL;

	if (clk == &s3c24xx_dclk0) {
	mask = S3C2410_DCLKCON_DCLK0_DIV_MASK \|
	S3C2410_DCLKCON_DCLK0_CMP_MASK;
	data = S3C2410_DCLKCON_DCLK0_DIV(div) \|
	S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
	} else if (clk == &s3c24xx_dclk1) {
	mask = S3C2410_DCLKCON_DCLK1_DIV_MASK \|
	S3C2410_DCLKCON_DCLK1_CMP_MASK;
	data = S3C2410_DCLKCON_DCLK1_DIV(div) \|
	S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
	} else
	return -EINVAL;

	clk->rate = clk_get_rate(clk->parent) / div;
	__raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) \| data),
	S3C24XX_DCLKCON);
	return clk->rate;
	}
	static int s3c24xx_clkout_setparent(struct clk clk, struct clk parent)
	{
	unsigned long mask;
	unsigned long source;

	/* calculate the MISCCR setting for the clock */

	if (parent == &clk_mpll)
	source = S3C2410_MISCCR_CLK0_MPLL;
	else if (parent == &clk_upll)
	source = S3C2410_MISCCR_CLK0_UPLL;
	else if (parent == &clk_f)
	source = S3C2410_MISCCR_CLK0_FCLK;
	else if (parent == &clk_h)
	source = S3C2410_MISCCR_CLK0_HCLK;
	else if (parent == &clk_p)
	source = S3C2410_MISCCR_CLK0_PCLK;
	else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
	source = S3C2410_MISCCR_CLK0_DCLK0;
	else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
	source = S3C2410_MISCCR_CLK0_DCLK0;
	else
	return -EINVAL;

	clk->parent = parent;

	if (clk == &s3c24xx_clkout0)
	mask = S3C2410_MISCCR_CLK0_MASK;
	else {
	source <<= 4;
	mask = S3C2410_MISCCR_CLK1_MASK;
	}

	s3c2410_modify_misccr(mask, source);
	return 0;
	}

	/* external clock definitions */

	static struct clk_ops dclk_ops = {
	.set_parent = s3c24xx_dclk_setparent,
	.set_rate = s3c24xx_set_dclk_rate,
	.round_rate = s3c24xx_round_dclk_rate,
	};

	struct clk s3c24xx_dclk0 = {
	.name = "dclk0",
	.ctrlbit = S3C2410_DCLKCON_DCLK0EN,
	.enable = s3c24xx_dclk_enable,
	.ops = &dclk_ops,
	};

	struct clk s3c24xx_dclk1 = {
	.name = "dclk1",
	.ctrlbit = S3C2410_DCLKCON_DCLK1EN,
	.enable = s3c24xx_dclk_enable,
	.ops = &dclk_ops,
	};

	static struct clk_ops clkout_ops = {
	.set_parent = s3c24xx_clkout_setparent,
	};

	struct clk s3c24xx_clkout0 = {
	.name = "clkout0",
	.ops = &clkout_ops,
	};

	struct clk s3c24xx_clkout1 = {
	.name = "clkout1",
	.ops = &clkout_ops,
	};

arch/arm/mach-s3c24xx/clock-s3c2410.c

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	/*
	* Copyright (c) 2006 Simtec Electronics
	* Ben Dooks <ben@simtec.co.uk>
	*
	* S3C2410,S3C2440,S3C2442 Clock control support
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License as published by
	* the Free Software Foundation; either version 2 of the License, or
	* (at your option) any later version.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* You should have received a copy of the GNU General Public License
	* along with this program; if not, write to the Free Software
	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	*/

	#include <linux/init.h>
	#include <linux/module.h>
	#include <linux/kernel.h>
	#include <linux/list.h>
	#include <linux/errno.h>
	#include <linux/err.h>
	#include <linux/device.h>
	#include <linux/clk.h>
	#include <linux/mutex.h>
	#include <linux/delay.h>
	#include <linux/serial_core.h>
	#include <linux/serial_s3c.h>
	#include <linux/io.h>

	#include <asm/mach/map.h>

	#include <mach/hardware.h>
	#include <mach/regs-clock.h>
	#include <mach/regs-gpio.h>

	#include <plat/clock.h>
	#include <plat/cpu.h>

	int s3c2410_clkcon_enable(struct clk *clk, int enable)
	{
	unsigned int clocks = clk->ctrlbit;
	unsigned long clkcon;

	clkcon = __raw_readl(S3C2410_CLKCON);

	if (enable)
	clkcon \|= clocks;
	else
	clkcon &= ~clocks;

	/* ensure none of the special function bits set */
	clkcon &= ~(S3C2410_CLKCON_IDLE\|S3C2410_CLKCON_POWER);

	__raw_writel(clkcon, S3C2410_CLKCON);

	return 0;
	}

	static int s3c2410_upll_enable(struct clk *clk, int enable)
	{
	unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
	unsigned long orig = clkslow;

	if (enable)
	clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
	else
	clkslow \|= S3C2410_CLKSLOW_UCLK_OFF;

	__raw_writel(clkslow, S3C2410_CLKSLOW);

	/* if we started the UPLL, then allow to settle */

	if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
	udelay(200);

	return 0;
	}

	/* standard clock definitions */

	static struct clk init_clocks_off[] = {
	{
	.name = "nand",
	.parent = &clk_h,
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2410_CLKCON_NAND,
	}, {
	.name = "sdi",
	.parent = &clk_p,
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2410_CLKCON_SDI,
	}, {
	.name = "adc",
	.parent = &clk_p,
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2410_CLKCON_ADC,
	}, {
	.name = "i2c",
	.parent = &clk_p,
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2410_CLKCON_IIC,
	}, {
	.name = "iis",
	.parent = &clk_p,
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2410_CLKCON_IIS,
	}, {
	.name = "spi",
	.parent = &clk_p,
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2410_CLKCON_SPI,
	}
	};

	static struct clk clk_lcd = {
	.name = "lcd",
	.parent = &clk_h,
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2410_CLKCON_LCDC,
	};

	static struct clk clk_gpio = {
	.name = "gpio",
	.parent = &clk_p,
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2410_CLKCON_GPIO,
	};

	static struct clk clk_usb_host = {
	.name = "usb-host",
	.parent = &clk_h,
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2410_CLKCON_USBH,
	};

	static struct clk clk_usb_device = {
	.name = "usb-device",
	.parent = &clk_h,
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2410_CLKCON_USBD,
	};

	static struct clk clk_timers = {
	.name = "timers",
	.parent = &clk_p,
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2410_CLKCON_PWMT,
	};

	struct clk s3c24xx_clk_uart0 = {
	.name = "uart",
	.devname = "s3c2410-uart.0",
	.parent = &clk_p,
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2410_CLKCON_UART0,
	};

	struct clk s3c24xx_clk_uart1 = {
	.name = "uart",
	.devname = "s3c2410-uart.1",
	.parent = &clk_p,
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2410_CLKCON_UART1,
	};

	struct clk s3c24xx_clk_uart2 = {
	.name = "uart",
	.devname = "s3c2410-uart.2",
	.parent = &clk_p,
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2410_CLKCON_UART2,
	};

	static struct clk clk_rtc = {
	.name = "rtc",
	.parent = &clk_p,
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2410_CLKCON_RTC,
	};

	static struct clk clk_watchdog = {
	.name = "watchdog",
	.parent = &clk_p,
	.ctrlbit = 0,
	};

	static struct clk clk_usb_bus_host = {
	.name = "usb-bus-host",
	.parent = &clk_usb_bus,
	};

	static struct clk clk_usb_bus_gadget = {
	.name = "usb-bus-gadget",
	.parent = &clk_usb_bus,
	};

	static struct clk *init_clocks[] = {
	&clk_lcd,
	&clk_gpio,
	&clk_usb_host,
	&clk_usb_device,
	&clk_timers,
	&s3c24xx_clk_uart0,
	&s3c24xx_clk_uart1,
	&s3c24xx_clk_uart2,
	&clk_rtc,
	&clk_watchdog,
	&clk_usb_bus_host,
	&clk_usb_bus_gadget,
	};

	/* s3c2410_baseclk_add()
	*
	* Add all the clocks used by the s3c2410 or compatible CPUs
	* such as the S3C2440 and S3C2442.
	*
	* We cannot use a system device as we are needed before any
	* of the init-calls that initialise the devices are actually
	* done.
	*/

	int __init s3c2410_baseclk_add(void)
	{
	unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
	unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
	struct clk *xtal;
	int ret;
	int ptr;

	clk_upll.enable = s3c2410_upll_enable;

	if (s3c24xx_register_clock(&clk_usb_bus) < 0)
	printk(KERN_ERR "failed to register usb bus clock\n");

	/* register clocks from clock array */

	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++) {
	struct clk *clkp = init_clocks[ptr];

	/* ensure that we note the clock state */

	clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;

	ret = s3c24xx_register_clock(clkp);
	if (ret < 0) {
	printk(KERN_ERR "Failed to register clock %s (%d)\n",
	clkp->name, ret);
	}
	}

	/* We must be careful disabling the clocks we are not intending to
	* be using at boot time, as subsystems such as the LCD which do
	* their own DMA requests to the bus can cause the system to lockup
	* if they where in the middle of requesting bus access.
	*
	* Disabling the LCD clock if the LCD is active is very dangerous,
	* and therefore the bootloader should be careful to not enable
	* the LCD clock if it is not needed.
	*/

	/* install (and disable) the clocks we do not need immediately */

	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	/* show the clock-slow value */

	xtal = clk_get(NULL, "xtal");

	printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
	print_mhz(clk_get_rate(xtal) /
	( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
	(clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
	(clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
	(clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");

	return 0;
	}

arch/arm/mach-s3c24xx/clock-s3c2440.c

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	/* linux/arch/arm/mach-s3c2440/clock.c
	*
	* Copyright (c) 2004-2005 Simtec Electronics
	* http://armlinux.simtec.co.uk/
	* Ben Dooks <ben@simtec.co.uk>
	*
	* S3C2440 Clock support
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License as published by
	* the Free Software Foundation; either version 2 of the License, or
	* (at your option) any later version.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* You should have received a copy of the GNU General Public License
	* along with this program; if not, write to the Free Software
	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	*/

	#include <linux/init.h>
	#include <linux/module.h>
	#include <linux/kernel.h>
	#include <linux/list.h>
	#include <linux/errno.h>
	#include <linux/err.h>
	#include <linux/device.h>
	#include <linux/interrupt.h>
	#include <linux/ioport.h>
	#include <linux/mutex.h>
	#include <linux/clk.h>
	#include <linux/io.h>
	#include <linux/serial_core.h>
	#include <linux/serial_s3c.h>

	#include <mach/hardware.h>
	#include <linux/atomic.h>
	#include <asm/irq.h>

	#include <mach/regs-clock.h>

	#include <plat/clock.h>
	#include <plat/cpu.h>

	/* S3C2440 extended clock support */

	static unsigned long s3c2440_camif_upll_round(struct clk *clk,
	unsigned long rate)
	{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	int div;

	if (rate > parent_rate)
	return parent_rate;

	/* note, we remove the +/- 1 calculations for the divisor */

	div = (parent_rate / rate) / 2;

	if (div < 1)
	div = 1;
	else if (div > 16)
	div = 16;

	return parent_rate / (div * 2);
	}

	static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
	{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);

	rate = s3c2440_camif_upll_round(clk, rate);

	camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL \| S3C2440_CAMDIVN_CAMCLK_MASK);

	if (rate != parent_rate) {
	camdivn \|= S3C2440_CAMDIVN_CAMCLK_SEL;
	camdivn \|= (((parent_rate / rate) / 2) - 1);
	}

	__raw_writel(camdivn, S3C2440_CAMDIVN);

	return 0;
	}

	static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
	{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);

	if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL))
	return parent_rate;

	camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK;

	return parent_rate / (camdivn + 1) / 2;
	}

	/* Extra S3C2440 clocks */

	static struct clk s3c2440_clk_cam = {
	.name = "camif",
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2440_CLKCON_CAMERA,
	};

	static struct clk s3c2440_clk_cam_upll = {
	.name = "camif-upll",
	.ops = &(struct clk_ops) {
	.set_rate = s3c2440_camif_upll_setrate,
	.get_rate = s3c2440_camif_upll_getrate,
	.round_rate = s3c2440_camif_upll_round,
	},
	};

	static struct clk s3c2440_clk_ac97 = {
	.name = "ac97",
	.enable = s3c2410_clkcon_enable,
	.ctrlbit = S3C2440_CLKCON_AC97,
	};

	#define S3C24XX_VA_UART0 (S3C_VA_UART)
	#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
	#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
	#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )

	static unsigned long s3c2440_fclk_n_getrate(struct clk *clk)
	{
	unsigned long ucon0, ucon1, ucon2, divisor;

	/* the fun of calculating the uart divisors on the s3c2440 */
	ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
	ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
	ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);

	ucon0 &= S3C2440_UCON0_DIVMASK;
	ucon1 &= S3C2440_UCON1_DIVMASK;
	ucon2 &= S3C2440_UCON2_DIVMASK;

	if (ucon0 != 0)
	divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
	else if (ucon1 != 0)
	divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
	else if (ucon2 != 0)
	divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
	else
	/* manual calims 44, seems to be 9 */
	divisor = 9;

	return clk_get_rate(clk->parent) / divisor;
	}

	static struct clk s3c2440_clk_fclk_n = {
	.name = "fclk_n",
	.parent = &clk_f,
	.ops = &(struct clk_ops) {
	.get_rate = s3c2440_fclk_n_getrate,
	},
	};

	static struct clk_lookup s3c2440_clk_lookup[] = {
	CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
	CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
	CLKDEV_INIT("s3c2440-uart.0", "uart", &s3c24xx_clk_uart0),
	CLKDEV_INIT("s3c2440-uart.1", "uart", &s3c24xx_clk_uart1),
	CLKDEV_INIT("s3c2440-uart.2", "uart", &s3c24xx_clk_uart2),
	CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll),
	};

	static int __init_refok s3c2440_clk_add(struct device dev, struct subsys_interface sif)
	{
	struct clk *clock_upll;
	struct clk *clock_h;
	struct clk *clock_p;

	clock_p = clk_get(NULL, "pclk");
	clock_h = clk_get(NULL, "hclk");
	clock_upll = clk_get(NULL, "upll");

	if (IS_ERR(clock_p) \|\| IS_ERR(clock_h) \|\| IS_ERR(clock_upll)) {
	printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
	return -EINVAL;
	}

	s3c2440_clk_cam.parent = clock_h;
	s3c2440_clk_ac97.parent = clock_p;
	s3c2440_clk_cam_upll.parent = clock_upll;
	s3c24xx_register_clock(&s3c2440_clk_fclk_n);

	s3c24xx_register_clock(&s3c2440_clk_ac97);
	s3c24xx_register_clock(&s3c2440_clk_cam);
	s3c24xx_register_clock(&s3c2440_clk_cam_upll);
	clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));

	clk_disable(&s3c2440_clk_ac97);
	clk_disable(&s3c2440_clk_cam);

	return 0;
	}

	static struct subsys_interface s3c2440_clk_interface = {
	.name = "s3c2440_clk",
	.subsys = &s3c2440_subsys,
	.add_dev = s3c2440_clk_add,
	};

	static __init int s3c24xx_clk_init(void)
	{
	return subsys_interface_register(&s3c2440_clk_interface);
	}

	arch_initcall(s3c24xx_clk_init);