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Commit dbf3b7dd authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS fixes from Ralf Baechle:
 "The pending MIPS fixes for 3.19.  All across the field and nothing
  particularly severe or dramatic"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (23 commits)
  IRQCHIP: mips-gic: Avoid rerouting timer IRQs for smp-cmp
  MIPS: Fix syscall_get_nr for the syscall exit tracing.
  MIPS: elf2ecoff: Ignore PT_MIPS_ABIFLAGS program headers.
  MIPS: elf2ecoff: Rewrite main processing loop to switch.
  MIPS: fork: Fix MSA/FPU/DSP context duplication race
  MIPS: Fix C0_Pagegrain[IEC] support.
  MIPS: traps: Fix inline asm ctc1 missing .set hardfloat
  MIPS: mipsregs.h: Add write_32bit_cp1_register()
  MIPS: Fix kernel lockup or crash after CPU offline/online
  MIPS: OCTEON: fix kernel crash when offlining a CPU
  MIPS: ARC: Fix build error.
  MIPS: IRQ: Fix disable_irq on CPU IRQs
  MIPS: smp-mt,smp-cmp: Enable all HW IRQs on secondary CPUs
  MIPS: Fix restart of indirect syscalls
  MIPS: ELF: fix loading o32 binaries on 64-bit kernels
  MIPS: mips-cm: Fix sparse warnings
  MIPS: Kconfig: Fix recursive dependency.
  MIPS: Compat: Fix build error if CONFIG_MIPS32_COMPAT but no compat ABI.
  MIPS: JZ4740: Fixup #include's (sparse)
  MIPS: Wire up execveat(2).
  ...
parents 9d82f5eb 1b6af71a

arch/mips/Kconfig

+10 −13
Original line number Original line Diff line number Diff line
@@ -2656,27 +2656,21 @@ config TRAD_SIGNALS 
	bool

	bool





config MIPS32_COMPAT

config MIPS32_COMPAT

	bool "Kernel support for Linux/MIPS 32-bit binary compatibility"

	bool

	depends on 64BIT

	help

	  Select this option if you want Linux/MIPS 32-bit binary

	  compatibility. Since all software available for Linux/MIPS is

	  currently 32-bit you should say Y here.





config COMPAT

config COMPAT

	bool

	bool

	depends on MIPS32_COMPAT

	select ARCH_WANT_OLD_COMPAT_IPC

	default y





config SYSVIPC_COMPAT

config SYSVIPC_COMPAT

	bool

	bool

	depends on COMPAT && SYSVIPC

	default y





config MIPS32_O32

config MIPS32_O32

	bool "Kernel support for o32 binaries"

	bool "Kernel support for o32 binaries"

	depends on MIPS32_COMPAT

	depends on 64BIT

	select ARCH_WANT_OLD_COMPAT_IPC

	select COMPAT

	select MIPS32_COMPAT

	select SYSVIPC_COMPAT if SYSVIPC

	help

	help

	  Select this option if you want to run o32 binaries.  These are pure

	  Select this option if you want to run o32 binaries.  These are pure

	  32-bit binaries as used by the 32-bit Linux/MIPS port.  Most of

	  32-bit binaries as used by the 32-bit Linux/MIPS port.  Most of
@@ -2686,7 +2680,10 @@ config MIPS32_O32 




config MIPS32_N32

config MIPS32_N32

	bool "Kernel support for n32 binaries"

	bool "Kernel support for n32 binaries"

	depends on MIPS32_COMPAT

	depends on 64BIT

	select COMPAT

	select MIPS32_COMPAT

	select SYSVIPC_COMPAT if SYSVIPC

	help

	help

	  Select this option if you want to run n32 binaries.  These are

	  Select this option if you want to run n32 binaries.  These are

	  64-bit binaries using 32-bit quantities for addressing and certain

	  64-bit binaries using 32-bit quantities for addressing and certain

arch/mips/boot/elf2ecoff.c

+36 −28
Original line number Original line Diff line number Diff line
@@ -50,6 +50,7 @@ 
 * Some extra ELF definitions

 * Some extra ELF definitions

 */

 */

#define PT_MIPS_REGINFO 	0x70000000	/* Register usage information */

#define PT_MIPS_REGINFO 	0x70000000	/* Register usage information */

#define PT_MIPS_ABIFLAGS	0x70000003	/* Records ABI related flags  */





/* -------------------------------------------------------------------- */

/* -------------------------------------------------------------------- */
@@ -349,17 +350,15 @@ int main(int argc, char *argv[]) 




	for (i = 0; i < ex.e_phnum; i++) {

	for (i = 0; i < ex.e_phnum; i++) {

		/* Section types we can ignore... */

		/* Section types we can ignore... */

		if (ph[i].p_type == PT_NULL || ph[i].p_type == PT_NOTE ||

		switch (ph[i].p_type) {

		    ph[i].p_type == PT_PHDR

		case PT_NULL:

		    || ph[i].p_type == PT_MIPS_REGINFO)

		case PT_NOTE:

		case PT_PHDR:

		case PT_MIPS_REGINFO:

		case PT_MIPS_ABIFLAGS:

			continue;

			continue;

		/* Section types we can't handle... */



		else if (ph[i].p_type != PT_LOAD) {

		case PT_LOAD:

			fprintf(stderr,

				"Program header %d type %d can't be converted.\n",

				ex.e_phnum, ph[i].p_type);

			exit(1);

		}

			/* Writable (data) segment? */

			/* Writable (data) segment? */

			if (ph[i].p_flags & PF_W) {

			if (ph[i].p_flags & PF_W) {

				struct sect ndata, nbss;

				struct sect ndata, nbss;
@@ -382,6 +381,15 @@ int main(int argc, char *argv[]) 
			/* Remember the lowest segment start address. */

			/* Remember the lowest segment start address. */

			if (ph[i].p_vaddr < cur_vma)

			if (ph[i].p_vaddr < cur_vma)

				cur_vma = ph[i].p_vaddr;

				cur_vma = ph[i].p_vaddr;

			break;



		default:

			/* Section types we can't handle... */

			fprintf(stderr,

				"Program header %d type %d can't be converted.\n",

				ex.e_phnum, ph[i].p_type);

			exit(1);

		}

	}

	}





	/* Sections must be in order to be converted... */

	/* Sections must be in order to be converted... */

arch/mips/cavium-octeon/smp.c

+0 −2
Original line number Original line Diff line number Diff line
@@ -240,9 +240,7 @@ static int octeon_cpu_disable(void) 




	set_cpu_online(cpu, false);

	set_cpu_online(cpu, false);

	cpu_clear(cpu, cpu_callin_map);

	cpu_clear(cpu, cpu_callin_map);

	local_irq_disable();

	octeon_fixup_irqs();

	octeon_fixup_irqs();

	local_irq_enable();





	flush_cache_all();

	flush_cache_all();

	local_flush_tlb_all();

	local_flush_tlb_all();

arch/mips/configs/malta_defconfig

+4 −12
Original line number Original line Diff line number Diff line
@@ -132,7 +132,6 @@ CONFIG_IP_NF_MATCH_ECN=m 
CONFIG_IP_NF_MATCH_TTL=m

CONFIG_IP_NF_MATCH_TTL=m

CONFIG_IP_NF_FILTER=m

CONFIG_IP_NF_FILTER=m

CONFIG_IP_NF_TARGET_REJECT=m

CONFIG_IP_NF_TARGET_REJECT=m

CONFIG_IP_NF_TARGET_ULOG=m

CONFIG_IP_NF_MANGLE=m

CONFIG_IP_NF_MANGLE=m

CONFIG_IP_NF_TARGET_CLUSTERIP=m

CONFIG_IP_NF_TARGET_CLUSTERIP=m

CONFIG_IP_NF_TARGET_ECN=m

CONFIG_IP_NF_TARGET_ECN=m
@@ -175,7 +174,6 @@ CONFIG_BRIDGE_EBT_MARK_T=m 
CONFIG_BRIDGE_EBT_REDIRECT=m

CONFIG_BRIDGE_EBT_REDIRECT=m

CONFIG_BRIDGE_EBT_SNAT=m

CONFIG_BRIDGE_EBT_SNAT=m

CONFIG_BRIDGE_EBT_LOG=m

CONFIG_BRIDGE_EBT_LOG=m

CONFIG_BRIDGE_EBT_ULOG=m

CONFIG_BRIDGE_EBT_NFLOG=m

CONFIG_BRIDGE_EBT_NFLOG=m

CONFIG_IP_SCTP=m

CONFIG_IP_SCTP=m

CONFIG_BRIDGE=m

CONFIG_BRIDGE=m
@@ -220,8 +218,6 @@ CONFIG_NET_ACT_SKBEDIT=m 
CONFIG_NET_CLS_IND=y

CONFIG_NET_CLS_IND=y

CONFIG_CFG80211=m

CONFIG_CFG80211=m

CONFIG_MAC80211=m

CONFIG_MAC80211=m

CONFIG_MAC80211_RC_PID=y

CONFIG_MAC80211_RC_DEFAULT_PID=y

CONFIG_MAC80211_MESH=y

CONFIG_MAC80211_MESH=y

CONFIG_RFKILL=m

CONFIG_RFKILL=m

CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"

CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
@@ -248,19 +244,13 @@ CONFIG_ATA_OVER_ETH=m 
CONFIG_IDE=y

CONFIG_IDE=y

CONFIG_BLK_DEV_IDECD=y

CONFIG_BLK_DEV_IDECD=y

CONFIG_IDE_GENERIC=y

CONFIG_IDE_GENERIC=y

CONFIG_BLK_DEV_GENERIC=y

CONFIG_BLK_DEV_PIIX=y

CONFIG_BLK_DEV_IT8213=m

CONFIG_BLK_DEV_TC86C001=m

CONFIG_RAID_ATTRS=m

CONFIG_RAID_ATTRS=m

CONFIG_SCSI=m

CONFIG_BLK_DEV_SD=y

CONFIG_BLK_DEV_SD=m

CONFIG_CHR_DEV_ST=m

CONFIG_CHR_DEV_ST=m

CONFIG_CHR_DEV_OSST=m

CONFIG_CHR_DEV_OSST=m

CONFIG_BLK_DEV_SR=m

CONFIG_BLK_DEV_SR=m

CONFIG_BLK_DEV_SR_VENDOR=y

CONFIG_BLK_DEV_SR_VENDOR=y

CONFIG_CHR_DEV_SG=m

CONFIG_CHR_DEV_SG=m

CONFIG_SCSI_MULTI_LUN=y

CONFIG_SCSI_CONSTANTS=y

CONFIG_SCSI_CONSTANTS=y

CONFIG_SCSI_LOGGING=y

CONFIG_SCSI_LOGGING=y

CONFIG_SCSI_SCAN_ASYNC=y

CONFIG_SCSI_SCAN_ASYNC=y
@@ -273,6 +263,8 @@ CONFIG_SCSI_AACRAID=m 
CONFIG_SCSI_AIC7XXX=m

CONFIG_SCSI_AIC7XXX=m

CONFIG_AIC7XXX_RESET_DELAY_MS=15000

CONFIG_AIC7XXX_RESET_DELAY_MS=15000

# CONFIG_AIC7XXX_DEBUG_ENABLE is not set

# CONFIG_AIC7XXX_DEBUG_ENABLE is not set

CONFIG_ATA=y

CONFIG_ATA_PIIX=y

CONFIG_MD=y

CONFIG_MD=y

CONFIG_BLK_DEV_MD=m

CONFIG_BLK_DEV_MD=m

CONFIG_MD_LINEAR=m

CONFIG_MD_LINEAR=m
@@ -340,6 +332,7 @@ CONFIG_UIO=m 
CONFIG_UIO_CIF=m

CONFIG_UIO_CIF=m

CONFIG_EXT2_FS=y

CONFIG_EXT2_FS=y

CONFIG_EXT3_FS=y

CONFIG_EXT3_FS=y

CONFIG_EXT4_FS=y

CONFIG_REISERFS_FS=m

CONFIG_REISERFS_FS=m

CONFIG_REISERFS_PROC_INFO=y

CONFIG_REISERFS_PROC_INFO=y

CONFIG_REISERFS_FS_XATTR=y

CONFIG_REISERFS_FS_XATTR=y
@@ -441,4 +434,3 @@ CONFIG_CRYPTO_SERPENT=m 
CONFIG_CRYPTO_TEA=m

CONFIG_CRYPTO_TEA=m

CONFIG_CRYPTO_TWOFISH=m

CONFIG_CRYPTO_TWOFISH=m

# CONFIG_CRYPTO_ANSI_CPRNG is not set
 
# CONFIG_CRYPTO_ANSI_CPRNG is not set
 
CONFIG_CRC16=m

arch/mips/include/asm/fpu.h

+26 −17
Original line number Original line Diff line number Diff line
@@ -64,7 +64,7 @@ static inline int __enable_fpu(enum fpu_mode mode) 
			return SIGFPE;

			return SIGFPE;





		/* set FRE */

		/* set FRE */

		write_c0_config5(read_c0_config5() | MIPS_CONF5_FRE);

		set_c0_config5(MIPS_CONF5_FRE);

		goto fr_common;

		goto fr_common;





	case FPU_64BIT:

	case FPU_64BIT:
@@ -74,8 +74,10 @@ static inline int __enable_fpu(enum fpu_mode mode) 
#endif

#endif

		/* fall through */

		/* fall through */

	case FPU_32BIT:

	case FPU_32BIT:

		if (cpu_has_fre) {

			/* clear FRE */

			/* clear FRE */

		write_c0_config5(read_c0_config5() & ~MIPS_CONF5_FRE);

			clear_c0_config5(MIPS_CONF5_FRE);

		}

fr_common:

fr_common:

		/* set CU1 & change FR appropriately */

		/* set CU1 & change FR appropriately */

		fr = (int)mode & FPU_FR_MASK;

		fr = (int)mode & FPU_FR_MASK;
@@ -182,9 +184,17 @@ static inline int init_fpu(void) 
	int ret = 0;

	int ret = 0;





	if (cpu_has_fpu) {

	if (cpu_has_fpu) {

		unsigned int config5;



		ret = __own_fpu();

		ret = __own_fpu();

		if (!ret) {

		if (ret)

			unsigned int config5 = read_c0_config5();

			return ret;



		if (!cpu_has_fre) {

			_init_fpu();



			return 0;

		}





		/*

		/*

		 * Ensure FRE is clear whilst running _init_fpu, since

		 * Ensure FRE is clear whilst running _init_fpu, since
@@ -192,7 +202,7 @@ static inline int init_fpu(void) 
		 * was set then we'll just end up initialising all 32

		 * was set then we'll just end up initialising all 32

		 * 64b registers.

		 * 64b registers.

		 */

		 */

			write_c0_config5(config5 & ~MIPS_CONF5_FRE);

		config5 = clear_c0_config5(MIPS_CONF5_FRE);

		enable_fpu_hazard();

		enable_fpu_hazard();





		_init_fpu();

		_init_fpu();
@@ -200,7 +210,6 @@ static inline int init_fpu(void) 
		/* Restore FRE */

		/* Restore FRE */

		write_c0_config5(config5);

		write_c0_config5(config5);

		enable_fpu_hazard();

		enable_fpu_hazard();

		}

	} else

	} else

		fpu_emulator_init_fpu();

		fpu_emulator_init_fpu();