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Commit db7c0659 authored by Shawn Guo's avatar Shawn Guo
Browse files

ARM: imx6sx: add BYPASS support for PLL clocks 



This is the same change for imx6sx clock driver as "ARM: imx6q: add BYPASS
support for PLL clocks" for imx6q.  The difference is that only anaclk1
is available on imx6sx.

Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent e90f4199

arch/arm/mach-imx/clk-imx6sx.c

+54 −9
Original line number Diff line number Diff line
@@ -81,6 +81,14 @@ static const char *lvds_sels[] = { 
	"arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",

	"dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2",

};

static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };

static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };

static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };

static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };

static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };

static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };

static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };

static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };



static struct clk *clks[IMX6SX_CLK_CLK_END];

static struct clk_onecell_data clk_data;
@@ -143,18 +151,54 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 
	clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");

	clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");



	/* Clock source from external clock via CLK1 PAD */

	clks[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);



	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");

	base = of_iomap(np, 0);

	WARN_ON(!base);



	clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));

	clks[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));

	clks[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));

	clks[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));

	clks[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));

	clks[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));

	clks[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));



	/*                                    type               name    parent_name        base         div_mask */

	clks[IMX6SX_CLK_PLL1_SYS]       = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1_sys",      "osc",        base,        0x7f);

	clks[IMX6SX_CLK_PLL2_BUS]       = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus",      "osc",        base + 0x30, 0x1);

	clks[IMX6SX_CLK_PLL3_USB_OTG]   = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3_usb_otg",  "osc",        base + 0x10, 0x3);

	clks[IMX6SX_CLK_PLL4_AUDIO]     = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4_audio",    "osc",        base + 0x70, 0x7f);

	clks[IMX6SX_CLK_PLL5_VIDEO]     = imx_clk_pllv3(IMX_PLLV3_AV,      "pll5_video",    "osc",        base + 0xa0, 0x7f);

	clks[IMX6SX_CLK_PLL6_ENET]      = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll6_enet",     "osc",        base + 0xe0, 0x3);

	clks[IMX6SX_CLK_PLL7_USB_HOST]  = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7_usb_host", "osc",        base + 0x20, 0x3);

	clks[IMX6SX_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1", "pll1_bypass_src", base + 0x00, 0x7f);

	clks[IMX6SX_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);

	clks[IMX6SX_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3", "pll3_bypass_src", base + 0x10, 0x3);

	clks[IMX6SX_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4", "pll4_bypass_src", base + 0x70, 0x7f);

	clks[IMX6SX_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV,      "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);

	clks[IMX6SX_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll6", "pll6_bypass_src", base + 0xe0, 0x3);

	clks[IMX6SX_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7", "pll7_bypass_src", base + 0x20, 0x3);



	clks[IMX6SX_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);

	clks[IMX6SX_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);

	clks[IMX6SX_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);

	clks[IMX6SX_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);

	clks[IMX6SX_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);

	clks[IMX6SX_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);

	clks[IMX6SX_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);



	/* Do not bypass PLLs initially */

	clk_set_parent(clks[IMX6SX_PLL1_BYPASS], clks[IMX6SX_CLK_PLL1]);

	clk_set_parent(clks[IMX6SX_PLL2_BYPASS], clks[IMX6SX_CLK_PLL2]);

	clk_set_parent(clks[IMX6SX_PLL3_BYPASS], clks[IMX6SX_CLK_PLL3]);

	clk_set_parent(clks[IMX6SX_PLL4_BYPASS], clks[IMX6SX_CLK_PLL4]);

	clk_set_parent(clks[IMX6SX_PLL5_BYPASS], clks[IMX6SX_CLK_PLL5]);

	clk_set_parent(clks[IMX6SX_PLL6_BYPASS], clks[IMX6SX_CLK_PLL6]);

	clk_set_parent(clks[IMX6SX_PLL7_BYPASS], clks[IMX6SX_CLK_PLL7]);



	clks[IMX6SX_CLK_PLL1_SYS]      = imx_clk_gate("pll1_sys",      "pll1_bypass", base + 0x00, 13);

	clks[IMX6SX_CLK_PLL2_BUS]      = imx_clk_gate("pll2_bus",      "pll2_bypass", base + 0x30, 13);

	clks[IMX6SX_CLK_PLL3_USB_OTG]  = imx_clk_gate("pll3_usb_otg",  "pll3_bypass", base + 0x10, 13);

	clks[IMX6SX_CLK_PLL4_AUDIO]    = imx_clk_gate("pll4_audio",    "pll4_bypass", base + 0x70, 13);

	clks[IMX6SX_CLK_PLL5_VIDEO]    = imx_clk_gate("pll5_video",    "pll5_bypass", base + 0xa0, 13);

	clks[IMX6SX_CLK_PLL6_ENET]     = imx_clk_gate("pll6_enet",     "pll6_bypass", base + 0xe0, 13);

	clks[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0xe0, 13);



	/*

	 * Bit 20 is the reserved and read-only bit, we do this only for:
@@ -176,7 +220,8 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 
	clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5);

	clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);



	clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate("lvds1_out", "lvds1_sel", base + 0x160, 10);

	clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));

	clks[IMX6SX_CLK_LVDS1_IN]  = imx_clk_gate_exclusive("lvds1_in",  "anaclk1",   base + 0x160, 12, BIT(10));



	clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,

			base + 0xe0, 0, 2, 0, clk_enet_ref_table,

include/dt-bindings/clock/imx6sx-clock.h

+24 −1
Original line number Diff line number Diff line
@@ -251,6 +251,29 @@ 
#define IMX6SX_CLK_SAI2_IPG		238

#define IMX6SX_CLK_ESAI_IPG		239

#define IMX6SX_CLK_ESAI_MEM		240

#define IMX6SX_CLK_CLK_END		241

#define IMX6SX_CLK_LVDS1_IN		241

#define IMX6SX_CLK_ANACLK1		242

#define IMX6SX_PLL1_BYPASS_SRC		243

#define IMX6SX_PLL2_BYPASS_SRC		244

#define IMX6SX_PLL3_BYPASS_SRC		245

#define IMX6SX_PLL4_BYPASS_SRC		246

#define IMX6SX_PLL5_BYPASS_SRC		247

#define IMX6SX_PLL6_BYPASS_SRC		248

#define IMX6SX_PLL7_BYPASS_SRC		249

#define IMX6SX_CLK_PLL1			250

#define IMX6SX_CLK_PLL2			251

#define IMX6SX_CLK_PLL3			252

#define IMX6SX_CLK_PLL4			253

#define IMX6SX_CLK_PLL5			254

#define IMX6SX_CLK_PLL6			255

#define IMX6SX_CLK_PLL7			256

#define IMX6SX_PLL1_BYPASS		257

#define IMX6SX_PLL2_BYPASS		258

#define IMX6SX_PLL3_BYPASS		259

#define IMX6SX_PLL4_BYPASS		260

#define IMX6SX_PLL5_BYPASS		261

#define IMX6SX_PLL6_BYPASS		262

#define IMX6SX_PLL7_BYPASS		263

#define IMX6SX_CLK_CLK_END		264



#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */