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Commit db3c47a3 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'omap-cleanup-part2-for-v3.6' of... 

Merge tag 'omap-cleanup-part2-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup2

From Tony Lindgren <tony@atomide.com>:
This branch contains more clean-up like changes and minor fixes for making
it easier to support new omap SoCs, such as omap5 and am33xx.

This branch has dependencies to earlier clean-up in omap-cleanup-for-v3.6
and  omap-devel-dmtimer-for-v3.6 branches, and also depends on the
omap-devel-am33xx-for-v3.6 branch, and are based on a merge of these
branches.

* tag 'omap-cleanup-part2-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap

:
  ARM: OMAP: sdrc: Fix the build break for OMAP4 only builds
  ARM: OMAP2+: dmtimer: cleanup fclk usage
  ARM: OMAP2+: Fix mismerge for omap_hwmod_get_main_clk() API
  ARM: OMAP2+: Remove unnecessary ifdef around __omap2_set_globals
  ARM: OMAP2+: am33xx: Change cpu_is_am33xx to soc_is_am33xx
  ARM: OMAP2+: am33xx: Make am33xx as a separate class
  ARM: OMAP2+: Move omap3 dpll ops to dpll3xxx.c
  ARM: OMAP2+: All OMAP2PLUS uses omap-device.o target so add one entry
  ARM: OMAP: dmtimer: use devm_ API and do some cleanup in probe()
  ARM: OMAP2+: hwmod code: add support to set dmadisable in hwmod framework
  ARM: OMAP2+: PRM/CM: Move the stubbed prm and cm functions to prcm.c file and make them __weak
  ARM: OMAP2+: hwmod: add omap_hwmod_get_main_clk() API
  ARM: OMAP3+: dpll: optimize noncore dpll locking logic
  ARM: OMAP3: control: add definition for CONTROL_CAMERA_PHY_CTRL
  ARM: OMAP2+: powerdomain code: Fix Wake-up power domain power status
  ARM: OMAP4: clockdomain/CM code: Update supported transition modes
  ARM: OMAP3/4: omap_hwmod: Add rstst_offs field to struct omap_hwmod_omap4_prcm
  ARM: OMAP2+: hwmod: Add new sysc_type3 into omap_hwmod required for am33xx

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 3f96a2d9 fb584511

arch/arm/mach-omap2/Kconfig

+11 −1
Original line number Diff line number Diff line
@@ -21,12 +21,16 @@ config ARCH_OMAP2PLUS_TYPICAL 
	help

	  Compile a kernel suitable for booting most boards



config SOC_HAS_OMAP2_SDRC

	bool "OMAP2 SDRAM Controller support"



config ARCH_OMAP2

	bool "TI OMAP2"

	depends on ARCH_OMAP2PLUS

	default y

	select CPU_V6

	select MULTI_IRQ_HANDLER

	select SOC_HAS_OMAP2_SDRC



config ARCH_OMAP3

	bool "TI OMAP3"
@@ -38,6 +42,7 @@ config ARCH_OMAP3 
	select PM_OPP if PM

	select ARM_CPU_SUSPEND if PM

	select MULTI_IRQ_HANDLER

	select SOC_HAS_OMAP2_SDRC



config ARCH_OMAP4

	bool "TI OMAP4"
@@ -64,16 +69,19 @@ config SOC_OMAP2420 
	depends on ARCH_OMAP2

	default y

	select OMAP_DM_TIMER

	select SOC_HAS_OMAP2_SDRC



config SOC_OMAP2430

	bool "OMAP2430 support"

	depends on ARCH_OMAP2

	default y

	select SOC_HAS_OMAP2_SDRC



config SOC_OMAP3430

	bool "OMAP3430 support"

	depends on ARCH_OMAP3

	default y

	select SOC_HAS_OMAP2_SDRC



config SOC_TI81XX

	bool "TI81XX support"
@@ -82,8 +90,10 @@ config SOC_TI81XX 


config SOC_AM33XX

	bool "AM33XX support"

	depends on ARCH_OMAP3

	default y

	select CPU_V7

	select ARM_CPU_SUSPEND if PM

	select MULTI_IRQ_HANDLER



config OMAP_PACKAGE_ZAF

       bool

arch/arm/mach-omap2/Makefile

+7 −1
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \

	 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o



omap-2-3-common				= irq.o sdrc.o

omap-2-3-common				= irq.o

hwmod-common				= omap_hwmod.o \

					  omap_hwmod_common_data.o

clock-common				= clock.o clock_common_data.o \
@@ -16,12 +16,14 @@ secure-common = omap-smc.o omap-secure.o 
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)

obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)

obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)

obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)



ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)

obj-y += mcbsp.o

endif



obj-$(CONFIG_TWL4030_CORE) += omap_twl.o

obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)	+= sdrc.o



# SMP support ONLY available for OMAP4
@@ -100,6 +102,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) 
obj-$(CONFIG_ARCH_OMAP3)		+= voltagedomains3xxx_data.o

obj-$(CONFIG_ARCH_OMAP4)		+= $(voltagedomain-common)

obj-$(CONFIG_ARCH_OMAP4)		+= voltagedomains44xx_data.o

obj-$(CONFIG_SOC_AM33XX)		+= $(voltagedomain-common)

obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o



# OMAP powerdomain framework
@@ -115,6 +118,7 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o 
obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common)

obj-$(CONFIG_ARCH_OMAP4)		+= powerdomain44xx.o

obj-$(CONFIG_ARCH_OMAP4)		+= powerdomains44xx_data.o

obj-$(CONFIG_SOC_AM33XX)		+= $(powerdomain-common)

obj-$(CONFIG_SOC_AM33XX)		+= powerdomain33xx.o

obj-$(CONFIG_SOC_AM33XX)		+= powerdomains33xx_data.o
@@ -132,6 +136,7 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o 
obj-$(CONFIG_ARCH_OMAP4)		+= $(clockdomain-common)

obj-$(CONFIG_ARCH_OMAP4)		+= clockdomain44xx.o

obj-$(CONFIG_ARCH_OMAP4)		+= clockdomains44xx_data.o

obj-$(CONFIG_SOC_AM33XX)		+= $(clockdomain-common)

obj-$(CONFIG_SOC_AM33XX)		+= clockdomain33xx.o

obj-$(CONFIG_SOC_AM33XX)		+= clockdomains33xx_data.o
@@ -151,6 +156,7 @@ obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o 
obj-$(CONFIG_ARCH_OMAP3)		+= clkt_iclk.o

obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common) clock44xx_data.o

obj-$(CONFIG_ARCH_OMAP4)		+= dpll3xxx.o dpll44xx.o

obj-$(CONFIG_SOC_AM33XX)		+= $(clock-common) dpll3xxx.o



# OMAP2 clock rate set data (old "OPP" data)

obj-$(CONFIG_SOC_OMAP2420)		+= opp2420_data.o

arch/arm/mach-omap2/clock.c

+0 −18
Original line number Diff line number Diff line
@@ -398,24 +398,6 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) 
	return omap2_clksel_set_parent(clk, new_parent);

}



/* OMAP3/4 non-CORE DPLL clkops */



#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)



const struct clkops clkops_omap3_noncore_dpll_ops = {

	.enable		= omap3_noncore_dpll_enable,

	.disable	= omap3_noncore_dpll_disable,

	.allow_idle	= omap3_dpll_allow_idle,

	.deny_idle	= omap3_dpll_deny_idle,

};



const struct clkops clkops_omap3_core_dpll_ops = {

	.allow_idle	= omap3_dpll_allow_idle,

	.deny_idle	= omap3_dpll_deny_idle,

};



#endif



/*

 * OMAP2+ clock reset and init functions

 */

arch/arm/mach-omap2/clock3xxx_data.c

+1 −1
Original line number Diff line number Diff line
@@ -3491,7 +3491,7 @@ int __init omap3xxx_clk_init(void) 
	} else if (cpu_is_ti816x()) {

		cpu_mask = RATE_IN_TI816X;

		cpu_clkflg = CK_TI816X;

	} else if (cpu_is_am33xx()) {

	} else if (soc_is_am33xx()) {

		cpu_mask = RATE_IN_AM33XX;

	} else if (cpu_is_ti814x()) {

		cpu_mask = RATE_IN_TI814X;

arch/arm/mach-omap2/clock44xx_data.c

+11 −11
Original line number Diff line number Diff line
@@ -3299,17 +3299,17 @@ static struct omap_clk omap44xx_clks[] = { 
	CLK(NULL,	"smartreflex_core_fck",		&smartreflex_core_fck,	CK_443X),

	CLK(NULL,	"smartreflex_iva_fck",		&smartreflex_iva_fck,	CK_443X),

	CLK(NULL,	"smartreflex_mpu_fck",		&smartreflex_mpu_fck,	CK_443X),

	CLK(NULL,	"gpt1_fck",			&timer1_fck,	CK_443X),

	CLK(NULL,	"gpt10_fck",			&timer10_fck,	CK_443X),

	CLK(NULL,	"gpt11_fck",			&timer11_fck,	CK_443X),

	CLK(NULL,	"gpt2_fck",			&timer2_fck,	CK_443X),

	CLK(NULL,	"gpt3_fck",			&timer3_fck,	CK_443X),

	CLK(NULL,	"gpt4_fck",			&timer4_fck,	CK_443X),

	CLK(NULL,	"gpt5_fck",			&timer5_fck,	CK_443X),

	CLK(NULL,	"gpt6_fck",			&timer6_fck,	CK_443X),

	CLK(NULL,	"gpt7_fck",			&timer7_fck,	CK_443X),

	CLK(NULL,	"gpt8_fck",			&timer8_fck,	CK_443X),

	CLK(NULL,	"gpt9_fck",			&timer9_fck,	CK_443X),

	CLK(NULL,	"timer1_fck",			&timer1_fck,	CK_443X),

	CLK(NULL,	"timer10_fck",			&timer10_fck,	CK_443X),

	CLK(NULL,	"timer11_fck",			&timer11_fck,	CK_443X),

	CLK(NULL,	"timer2_fck",			&timer2_fck,	CK_443X),

	CLK(NULL,	"timer3_fck",			&timer3_fck,	CK_443X),

	CLK(NULL,	"timer4_fck",			&timer4_fck,	CK_443X),

	CLK(NULL,	"timer5_fck",			&timer5_fck,	CK_443X),

	CLK(NULL,	"timer6_fck",			&timer6_fck,	CK_443X),

	CLK(NULL,	"timer7_fck",			&timer7_fck,	CK_443X),

	CLK(NULL,	"timer8_fck",			&timer8_fck,	CK_443X),

	CLK(NULL,	"timer9_fck",			&timer9_fck,	CK_443X),

	CLK(NULL,	"uart1_fck",			&uart1_fck,	CK_443X),

	CLK(NULL,	"uart2_fck",			&uart2_fck,	CK_443X),

	CLK(NULL,	"uart3_fck",			&uart3_fck,	CK_443X),