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Commit d9e29649 authored by Matt Reimer's avatar Matt Reimer Committed by Russell King
Browse files

[ARM] 3029/1: Add HWUART support for PXA 255/26x 

Patch from Matt Reimer

Adds support for HWUART on PXA 255 / 26x. This patch originally came from
http://svn.rungie.com/svn/gumstix-buildroot/trunk/sources/kernel-patches/000-gumstix-hwuart.patch


and has been tweaked by me.

Signed-off-by: default avatarMatt Reimer <mreimer@vpop.net>
Signed-off-by: default avatarNicolas Pitre <nico@cam.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 80a18573

arch/arm/mach-pxa/generic.c

+17 −1
Original line number Diff line number Diff line
@@ -253,6 +253,10 @@ static struct platform_device stuart_device = { 
	.name		= "pxa2xx-uart",

	.id		= 2,

};

static struct platform_device hwuart_device = {

	.name		= "pxa2xx-uart",

	.id		= 3,

};



static struct resource i2c_resources[] = {

	{
@@ -310,7 +314,19 @@ static struct platform_device *devices[] __initdata = { 


static int __init pxa_init(void)

{

	return platform_add_devices(devices, ARRAY_SIZE(devices));

	int cpuid, ret;



	ret = platform_add_devices(devices, ARRAY_SIZE(devices));

	if (ret)

		return ret;



	/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */

	cpuid = read_cpuid(CPUID_ID);

	if (((cpuid >> 4) & 0xfff) == 0x2d0 ||

	    ((cpuid >> 4) & 0xfff) == 0x290)

		ret = platform_device_register(&hwuart_device);



	return ret;

}



subsys_initcall(pxa_init);

drivers/serial/pxa.c

+20 −1
Original line number Diff line number Diff line
@@ -358,6 +358,9 @@ static int serial_pxa_startup(struct uart_port *port) 
	unsigned long flags;

	int retval;



	if (port->line == 3) /* HWUART */

		up->mcr |= UART_MCR_AFE;

	else

	up->mcr = 0;



	/*
@@ -481,8 +484,10 @@ serial_pxa_set_termios(struct uart_port *port, struct termios *termios, 


	if ((up->port.uartclk / quot) < (2400 * 16))

		fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;

	else

	else if ((up->port.uartclk / quot) < (230400 * 16))

		fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;

	else

		fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;



	/*

	 * Ok, we're now changing the port state.  Do it with
@@ -772,6 +777,20 @@ static struct uart_pxa_port serial_pxa_ports[] = { 
		.ops		= &serial_pxa_pops,

		.line		= 2,

	},

  }, {  /* HWUART */

	.name	= "HWUART",

	.cken	= CKEN4_HWUART,

	.port = {

		.type		= PORT_PXA,

		.iotype		= UPIO_MEM,

		.membase	= (void *)&HWUART,

		.mapbase	= __PREG(HWUART),

		.irq		= IRQ_HWUART,

		.uartclk	= 921600 * 16,

		.fifosize	= 64,

		.ops		= &serial_pxa_pops,

		.line		= 3,

	},

  }

};

include/asm-arm/arch-pxa/pxa-regs.h

+33 −0
Original line number Diff line number Diff line
@@ -326,6 +326,25 @@ 
#define STDLL		__REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */

#define STDLH		__REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */



/* Hardware UART (HWUART) */

#define HWUART		HWRBR

#define HWRBR		__REG(0x41600000)  /* Receive Buffer Register (read only) */

#define HWTHR		__REG(0x41600000)  /* Transmit Holding Register (write only) */

#define HWIER		__REG(0x41600004)  /* Interrupt Enable Register (read/write) */

#define HWIIR		__REG(0x41600008)  /* Interrupt ID Register (read only) */

#define HWFCR		__REG(0x41600008)  /* FIFO Control Register (write only) */

#define HWLCR		__REG(0x4160000C)  /* Line Control Register (read/write) */

#define HWMCR		__REG(0x41600010)  /* Modem Control Register (read/write) */

#define HWLSR		__REG(0x41600014)  /* Line Status Register (read only) */

#define HWMSR		__REG(0x41600018)  /* Modem Status Register (read only) */

#define HWSPR		__REG(0x4160001C)  /* Scratch Pad Register (read/write) */

#define HWISR		__REG(0x41600020)  /* Infrared Selection Register (read/write) */

#define HWFOR		__REG(0x41600024)  /* Receive FIFO Occupancy Register (read only) */

#define HWABR		__REG(0x41600028)  /* Auto-Baud Control Register (read/write) */

#define HWACR		__REG(0x4160002C)  /* Auto-Baud Count Register (read only) */

#define HWDLL		__REG(0x41600000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */

#define HWDLH		__REG(0x41600004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */



#define IER_DMAE	(1 << 7)	/* DMA Requests Enable */

#define IER_UUE		(1 << 6)	/* UART Unit Enable */

#define IER_NRZE	(1 << 5)	/* NRZ coding Enable */
@@ -1250,9 +1269,13 @@ 
#define GPIO40_FFDTR		40	/* FFUART data terminal Ready */

#define GPIO41_FFRTS		41	/* FFUART request to send */

#define GPIO42_BTRXD		42	/* BTUART receive data */

#define GPIO42_HWRXD		42	/* HWUART receive data */

#define GPIO43_BTTXD		43	/* BTUART transmit data */

#define GPIO43_HWTXD		43	/* HWUART transmit data */

#define GPIO44_BTCTS		44	/* BTUART clear to send */

#define GPIO44_HWCTS		44	/* HWUART clear to send */

#define GPIO45_BTRTS		45	/* BTUART request to send */

#define GPIO45_HWRTS		45	/* HWUART request to send */

#define GPIO45_AC97_SYSCLK	45	/* AC97 System Clock */

#define GPIO46_ICPRXD		46	/* ICP receive data */

#define GPIO46_STRXD		46	/* STD_UART receive data */
@@ -1378,17 +1401,26 @@ 
#define GPIO40_FFDTR_MD		(40 | GPIO_ALT_FN_2_OUT)

#define GPIO41_FFRTS_MD		(41 | GPIO_ALT_FN_2_OUT)

#define GPIO42_BTRXD_MD		(42 | GPIO_ALT_FN_1_IN)

#define GPIO42_HWRXD_MD		(42 | GPIO_ALT_FN_3_IN)

#define GPIO43_BTTXD_MD		(43 | GPIO_ALT_FN_2_OUT)

#define GPIO43_HWTXD_MD		(43 | GPIO_ALT_FN_3_OUT)

#define GPIO44_BTCTS_MD		(44 | GPIO_ALT_FN_1_IN)

#define GPIO44_HWCTS_MD		(44 | GPIO_ALT_FN_3_IN)

#define GPIO45_BTRTS_MD		(45 | GPIO_ALT_FN_2_OUT)

#define GPIO45_HWRTS_MD		(45 | GPIO_ALT_FN_3_OUT)

#define GPIO45_SYSCLK_AC97_MD		(45 | GPIO_ALT_FN_1_OUT)

#define GPIO46_ICPRXD_MD	(46 | GPIO_ALT_FN_1_IN)

#define GPIO46_STRXD_MD		(46 | GPIO_ALT_FN_2_IN)

#define GPIO47_ICPTXD_MD	(47 | GPIO_ALT_FN_2_OUT)

#define GPIO47_STTXD_MD		(47 | GPIO_ALT_FN_1_OUT)

#define GPIO48_nPOE_MD		(48 | GPIO_ALT_FN_2_OUT)

#define GPIO48_HWTXD_MD         (48 | GPIO_ALT_FN_1_OUT)

#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)

#define GPIO49_HWRXD_MD		(49 | GPIO_ALT_FN_1_IN)

#define GPIO49_nPWE_MD		(49 | GPIO_ALT_FN_2_OUT)

#define GPIO50_nPIOR_MD		(50 | GPIO_ALT_FN_2_OUT)

#define GPIO50_HWCTS_MD         (50 | GPIO_ALT_FN_1_IN)

#define GPIO51_HWRTS_MD         (51 | GPIO_ALT_FN_1_OUT)

#define GPIO51_nPIOW_MD		(51 | GPIO_ALT_FN_2_OUT)

#define GPIO52_nPCE_1_MD	(52 | GPIO_ALT_FN_2_OUT)

#define GPIO53_nPCE_2_MD	(53 | GPIO_ALT_FN_2_OUT)
@@ -1763,6 +1795,7 @@ 
#define CKEN7_BTUART	(1 << 7)	/* BTUART Unit Clock Enable */

#define CKEN6_FFUART	(1 << 6)	/* FFUART Unit Clock Enable */

#define CKEN5_STUART	(1 << 5)	/* STUART Unit Clock Enable */

#define CKEN4_HWUART	(1 << 4)	/* HWUART Unit Clock Enable */

#define CKEN4_SSP3	(1 << 4)	/* SSP3 Unit Clock Enable */

#define CKEN3_SSP	(1 << 3)	/* SSP Unit Clock Enable */

#define CKEN3_SSP2	(1 << 3)	/* SSP2 Unit Clock Enable */

include/asm-arm/arch-pxa/uncompress.h

+1 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#define FFUART		((volatile unsigned long *)0x40100000)

#define BTUART		((volatile unsigned long *)0x40200000)

#define STUART		((volatile unsigned long *)0x40700000)

#define HWUART		((volatile unsigned long *)0x41600000)



#define UART		FFUART