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Commit d74362c9 authored by Keith Packard's avatar Keith Packard
Browse files

drm/i915: Flush other plane register writes 



Writes to the plane control register are buffered in the chip until a
write to the DSPADDR (pre-965) or DSPSURF (post-965) register occurs.

This patch adds flushes in:

	intel_enable_plane
	gen6_init_clock_gating
	ivybridge_init_clock_gating

Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
parent 2704cf5f

drivers/gpu/drm/i915/intel_display.c

+18 −13
Original line number Original line Diff line number Diff line
@@ -1290,6 +1290,17 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv, 
	intel_wait_for_pipe_off(dev_priv->dev, pipe);

	intel_wait_for_pipe_off(dev_priv->dev, pipe);

}

}





/*

 * Plane regs are double buffered, going from enabled->disabled needs a

 * trigger in order to latch.  The display address reg provides this.

 */

static void intel_flush_display_plane(struct drm_i915_private *dev_priv,

				      enum plane plane)

{

	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));

	I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));

}



/**

/**

 * intel_enable_plane - enable a display plane on a given pipe

 * intel_enable_plane - enable a display plane on a given pipe

 * @dev_priv: i915 private structure

 * @dev_priv: i915 private structure
@@ -1313,20 +1324,10 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv, 
		return;

		return;





	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);

	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);

	intel_flush_display_plane(dev_priv, plane);

	intel_wait_for_vblank(dev_priv->dev, pipe);

	intel_wait_for_vblank(dev_priv->dev, pipe);

}

}





/*

 * Plane regs are double buffered, going from enabled->disabled needs a

 * trigger in order to latch.  The display address reg provides this.

 */

static void intel_flush_display_plane(struct drm_i915_private *dev_priv,

				      enum plane plane)

{

	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));

	I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));

}



/**

/**

 * intel_disable_plane - disable a display plane

 * intel_disable_plane - disable a display plane

 * @dev_priv: i915 private structure

 * @dev_priv: i915 private structure
@@ -7418,10 +7419,12 @@ static void gen6_init_clock_gating(struct drm_device *dev) 
		   ILK_DPARB_CLK_GATE  |

		   ILK_DPARB_CLK_GATE  |

		   ILK_DPFD_CLK_GATE);

		   ILK_DPFD_CLK_GATE);





	for_each_pipe(pipe)

	for_each_pipe(pipe) {

		I915_WRITE(DSPCNTR(pipe),

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |

			   I915_READ(DSPCNTR(pipe)) |

			   DISPPLANE_TRICKLE_FEED_DISABLE);

			   DISPPLANE_TRICKLE_FEED_DISABLE);

		intel_flush_display_plane(dev_priv, pipe);

	}

}

}





static void ivybridge_init_clock_gating(struct drm_device *dev)

static void ivybridge_init_clock_gating(struct drm_device *dev)
@@ -7438,10 +7441,12 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 




	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);

	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);





	for_each_pipe(pipe)

	for_each_pipe(pipe) {

		I915_WRITE(DSPCNTR(pipe),

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |

			   I915_READ(DSPCNTR(pipe)) |

			   DISPPLANE_TRICKLE_FEED_DISABLE);

			   DISPPLANE_TRICKLE_FEED_DISABLE);

		intel_flush_display_plane(dev_priv, pipe);

	}

}

}





static void g4x_init_clock_gating(struct drm_device *dev)

static void g4x_init_clock_gating(struct drm_device *dev)