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Commit d5ff89a8 authored by Peter De Schrijver's avatar Peter De Schrijver
Browse files

clk: tegra: simplify periph clock data 



This patch determines the register bank for clock enable/disable and reset
based on the clock ID instead of hardcoding it in the tables describing the
clocks. This results in less data to be maintained in the tables, making the
code easier to understand. The full benefit of the change will be realized once
also other clocktypes will be table based.

Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
parent 00c674e4

drivers/clk/tegra/clk-periph-gate.c

+6 −2
Original line number Diff line number Diff line
@@ -151,12 +151,16 @@ const struct clk_ops tegra_clk_periph_gate_ops = { 


struct clk *tegra_clk_register_periph_gate(const char *name,

		const char *parent_name, u8 gate_flags, void __iomem *clk_base,

		unsigned long flags, int clk_num,

		struct tegra_clk_periph_regs *pregs, int *enable_refcnt)

		unsigned long flags, int clk_num, int *enable_refcnt)

{

	struct tegra_clk_periph_gate *gate;

	struct clk *clk;

	struct clk_init_data init;

	struct tegra_clk_periph_regs *pregs;



	pregs = get_reg_bank(clk_num);

	if (!pregs)

		return ERR_PTR(-EINVAL);



	gate = kzalloc(sizeof(*gate), GFP_KERNEL);

	if (!gate) {

drivers/clk/tegra/clk-periph.c

+6 −0
Original line number Diff line number Diff line
@@ -178,6 +178,7 @@ static struct clk *_tegra_clk_register_periph(const char *name, 
{

	struct clk *clk;

	struct clk_init_data init;

	struct tegra_clk_periph_regs *bank;



	init.name = name;

	init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
@@ -185,12 +186,17 @@ static struct clk *_tegra_clk_register_periph(const char *name, 
	init.parent_names = parent_names;

	init.num_parents = num_parents;



	bank = get_reg_bank(periph->gate.clk_num);

	if (!bank)

		return ERR_PTR(-EINVAL);



	/* Data in .init is copied by clk_register(), so stack variable OK */

	periph->hw.init = &init;

	periph->magic = TEGRA_CLK_PERIPH_MAGIC;

	periph->mux.reg = clk_base + offset;

	periph->divider.reg = div ? (clk_base + offset) : NULL;

	periph->gate.clk_base = clk_base;

	periph->gate.regs = bank;



	clk = clk_register(NULL, &periph->hw);

	if (IS_ERR(clk))

drivers/clk/tegra/clk-tegra114.c

+141 −235

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drivers/clk/tegra/clk-tegra20.c

+82 −138

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drivers/clk/tegra/clk-tegra30.c

+116 −201

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