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Commit d423421c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge master.kernel.org:/home/rmk/linux-2.6-arm 

* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 3353/1: NAS100d: protect  nas100d_power_exit() with machine_is_nas100d()
  [ARM] 3352/1: DSB required for the completion of a TLB maintenance operation
parents 850a9a4e 744bfe4c

arch/arm/Kconfig

+1 −1
Original line number Original line Diff line number Diff line
@@ -78,7 +78,7 @@ menu "System Type" 




choice

choice

	prompt "ARM system type"

	prompt "ARM system type"

	default ARCH_RPC

	default ARCH_VERSATILE





config ARCH_CLPS7500

config ARCH_CLPS7500

	bool "Cirrus-CL-PS7500FE"

	bool "Cirrus-CL-PS7500FE"

arch/arm/mach-ixp4xx/nas100d-power.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -56,6 +56,9 @@ static int __init nas100d_power_init(void) 




static void __exit nas100d_power_exit(void)

static void __exit nas100d_power_exit(void)

{

{

	if (!(machine_is_nas100d()))

		return;



	free_irq(NAS100D_RB_IRQ, NULL);

	free_irq(NAS100D_RB_IRQ, NULL);

}

}

arch/arm/mm/tlb-v6.S

+1 −0
Original line number Original line Diff line number Diff line
@@ -80,6 +80,7 @@ ENTRY(v6wbi_flush_kern_tlb_range) 
	add	r0, r0, #PAGE_SZ

	add	r0, r0, #PAGE_SZ

	cmp	r0, r1

	cmp	r0, r1

	blo	1b

	blo	1b

	mcr	p15, 0, r2, c7, c10, 4		@ data synchronization barrier

	mov	pc, lr

	mov	pc, lr





	.section ".text.init", #alloc, #execinstr

	.section ".text.init", #alloc, #execinstr

include/asm-arm/tlbflush.h

+6 −0
Original line number Original line Diff line number Diff line
@@ -340,6 +340,12 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) 
		asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));

		asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));

	if (tlb_flag(TLB_V6_I_PAGE))

	if (tlb_flag(TLB_V6_I_PAGE))

		asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));

		asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));



	/* The ARM ARM states that the completion of a TLB maintenance

	 * operation is only guaranteed by a DSB instruction

	 */

	if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE))

		asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));

}

}





/*

/*