Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d415fa1b authored by Mugunthan V N's avatar Mugunthan V N Committed by David S. Miller
Browse files

drivers: net: cpsw-phy-sel: add dra7xx support for phy sel 



Add dra7xx support for selecting the phy mode which is present in control
module of dra7xx SoC

Signed-off-by: default avatarMugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 84ef36bd

Documentation/devicetree/bindings/net/cpsw-phy-sel.txt

+2 −1
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ TI CPSW Phy mode Selection Device Tree Bindings 
-----------------------------------------------



Required properties:

- compatible		: Should be "ti,am3352-cpsw-phy-sel"

- compatible		: Should be "ti,am3352-cpsw-phy-sel" for am335x platform and

			  "ti,dra7xx-cpsw-phy-sel" for dra7xx platform

- reg			: physical base address and size of the cpsw

			  registers map

- reg-names		: names of the register map given in "reg" node

drivers/net/ethernet/ti/cpsw-phy-sel.c

+56 −1
Original line number Diff line number Diff line
@@ -29,6 +29,8 @@ 
#define AM33XX_GMII_SEL_RMII2_IO_CLK_EN	BIT(7)

#define AM33XX_GMII_SEL_RMII1_IO_CLK_EN	BIT(6)



#define GMII_SEL_MODE_MASK		0x3



struct cpsw_phy_sel_priv {

	struct device	*dev;

	u32 __iomem	*gmii_sel;
@@ -65,7 +67,7 @@ static void cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv *priv, 
		break;

	};



	mask = 0x3 << (slave * 2) | BIT(slave + 6);

	mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);

	mode <<= slave * 2;



	if (priv->rmii_clock_external) {
@@ -81,6 +83,55 @@ static void cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv *priv, 
	writel(reg, priv->gmii_sel);

}



static void cpsw_gmii_sel_dra7xx(struct cpsw_phy_sel_priv *priv,

				 phy_interface_t phy_mode, int slave)

{

	u32 reg;

	u32 mask;

	u32 mode = 0;



	reg = readl(priv->gmii_sel);



	switch (phy_mode) {

	case PHY_INTERFACE_MODE_RMII:

		mode = AM33XX_GMII_SEL_MODE_RMII;

		break;



	case PHY_INTERFACE_MODE_RGMII:

	case PHY_INTERFACE_MODE_RGMII_ID:

	case PHY_INTERFACE_MODE_RGMII_RXID:

	case PHY_INTERFACE_MODE_RGMII_TXID:

		mode = AM33XX_GMII_SEL_MODE_RGMII;

		break;



	case PHY_INTERFACE_MODE_MII:

	default:

		mode = AM33XX_GMII_SEL_MODE_MII;

		break;

	};



	switch (slave) {

	case 0:

		mask = GMII_SEL_MODE_MASK;

		break;

	case 1:

		mask = GMII_SEL_MODE_MASK << 4;

		mode <<= 4;

		break;

	default:

		dev_err(priv->dev, "invalid slave number...\n");

		return;

	}



	if (priv->rmii_clock_external)

		dev_err(priv->dev, "RMII External clock is not supported\n");



	reg &= ~mask;

	reg |= mode;



	writel(reg, priv->gmii_sel);

}



static struct platform_driver cpsw_phy_sel_driver;

static int match(struct device *dev, void *data)

{
@@ -112,6 +163,10 @@ static const struct of_device_id cpsw_phy_sel_id_table[] = { 
		.compatible	= "ti,am3352-cpsw-phy-sel",

		.data		= &cpsw_gmii_sel_am3352,

	},

	{

		.compatible	= "ti,dra7xx-cpsw-phy-sel",

		.data		= &cpsw_gmii_sel_dra7xx,

	},

	{}

};

MODULE_DEVICE_TABLE(of, cpsw_phy_sel_id_table);