Loading drivers/gpu/drm/i915/intel_dp.c +14 −6 Original line number Diff line number Diff line Loading @@ -1335,10 +1335,16 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) u32 reg; uint32_t DP = intel_dp->DP; /* Enable output, wait for it to become active */ /* * On CPT we have to enable the port in training pattern 1, which * will happen below in intel_dp_set_link_train. Otherwise, enable * the port and wait for it to become active. */ if (!HAS_PCH_CPT(dev)) { I915_WRITE(intel_dp->output_reg, intel_dp->DP); POSTING_READ(intel_dp->output_reg); intel_wait_for_vblank(dev, intel_crtc->pipe); } /* Write the link configuration data */ intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, Loading Loading @@ -1371,7 +1377,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) reg = DP | DP_LINK_TRAIN_PAT_1; if (!intel_dp_set_link_train(intel_dp, reg, DP_TRAINING_PATTERN_1)) DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE)) break; /* Set training pattern 1 */ Loading Loading @@ -1446,7 +1453,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) /* channel eq pattern */ if (!intel_dp_set_link_train(intel_dp, reg, DP_TRAINING_PATTERN_2)) DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE)) break; udelay(400); Loading drivers/gpu/drm/i915/intel_panel.c +4 −0 Original line number Diff line number Diff line Loading @@ -83,11 +83,15 @@ intel_pch_panel_fitting(struct drm_device *dev, u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; if (scaled_width > scaled_height) { /* pillar */ width = scaled_height / mode->vdisplay; if (width & 1) width++; x = (adjusted_mode->hdisplay - width + 1) / 2; y = 0; height = adjusted_mode->vdisplay; } else if (scaled_width < scaled_height) { /* letter */ height = scaled_width / mode->hdisplay; if (height & 1) height++; y = (adjusted_mode->vdisplay - height + 1) / 2; x = 0; width = adjusted_mode->hdisplay; Loading Loading
drivers/gpu/drm/i915/intel_dp.c +14 −6 Original line number Diff line number Diff line Loading @@ -1335,10 +1335,16 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) u32 reg; uint32_t DP = intel_dp->DP; /* Enable output, wait for it to become active */ /* * On CPT we have to enable the port in training pattern 1, which * will happen below in intel_dp_set_link_train. Otherwise, enable * the port and wait for it to become active. */ if (!HAS_PCH_CPT(dev)) { I915_WRITE(intel_dp->output_reg, intel_dp->DP); POSTING_READ(intel_dp->output_reg); intel_wait_for_vblank(dev, intel_crtc->pipe); } /* Write the link configuration data */ intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, Loading Loading @@ -1371,7 +1377,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) reg = DP | DP_LINK_TRAIN_PAT_1; if (!intel_dp_set_link_train(intel_dp, reg, DP_TRAINING_PATTERN_1)) DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE)) break; /* Set training pattern 1 */ Loading Loading @@ -1446,7 +1453,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) /* channel eq pattern */ if (!intel_dp_set_link_train(intel_dp, reg, DP_TRAINING_PATTERN_2)) DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE)) break; udelay(400); Loading
drivers/gpu/drm/i915/intel_panel.c +4 −0 Original line number Diff line number Diff line Loading @@ -83,11 +83,15 @@ intel_pch_panel_fitting(struct drm_device *dev, u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; if (scaled_width > scaled_height) { /* pillar */ width = scaled_height / mode->vdisplay; if (width & 1) width++; x = (adjusted_mode->hdisplay - width + 1) / 2; y = 0; height = adjusted_mode->vdisplay; } else if (scaled_width < scaled_height) { /* letter */ height = scaled_width / mode->hdisplay; if (height & 1) height++; y = (adjusted_mode->vdisplay - height + 1) / 2; x = 0; width = adjusted_mode->hdisplay; Loading