Loading arch/arm/mach-omap2/clock24xx.c +5 −5 Original line number Original line Diff line number Diff line Loading @@ -103,10 +103,10 @@ static struct omap_clk omap24xx_clks[] = { CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), /* DSS domain clocks */ /* DSS domain clocks */ CLK(NULL, "dss_ick", &dss_ick, CK_243X | CK_242X), CLK("omapfb", "ick", &dss_ick, CK_243X | CK_242X), CLK(NULL, "dss1_fck", &dss1_fck, CK_243X | CK_242X), CLK("omapfb", "dss1_fck", &dss1_fck, CK_243X | CK_242X), CLK(NULL, "dss2_fck", &dss2_fck, CK_243X | CK_242X), CLK("omapfb", "dss2_fck", &dss2_fck, CK_243X | CK_242X), CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X | CK_242X), CLK("omapfb", "tv_fck", &dss_54m_fck, CK_243X | CK_242X), /* L3 domain clocks */ /* L3 domain clocks */ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), Loading Loading @@ -206,7 +206,7 @@ static struct omap_clk omap24xx_clks[] = { CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), Loading arch/arm/mach-omap2/clock34xx.c +6 −6 Original line number Original line Diff line number Diff line Loading @@ -157,7 +157,7 @@ static struct omap_clk omap34xx_clks[] = { CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X), CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X), CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X), CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X), CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X), CLK("musb_hdrc", "ick", &hsotgusb_ick, CK_343X), CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), Loading Loading @@ -197,11 +197,11 @@ static struct omap_clk omap34xx_clks[] = { CLK("omap_rng", "ick", &rng_ick, CK_343X), CLK("omap_rng", "ick", &rng_ick, CK_343X), CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), CLK(NULL, "des1_ick", &des1_ick, CK_343X), CLK(NULL, "des1_ick", &des1_ick, CK_343X), CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X), CLK("omapfb", "dss1_fck", &dss1_alwon_fck, CK_343X), CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X), CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X), CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X), CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X), CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X), CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X), CLK(NULL, "dss_ick", &dss_ick, CK_343X), CLK("omapfb", "ick", &dss_ick, CK_343X), CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), CLK(NULL, "cam_ick", &cam_ick, CK_343X), CLK(NULL, "cam_ick", &cam_ick, CK_343X), CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), Loading arch/arm/mach-omap2/clock34xx.h +6 −6 Original line number Original line Diff line number Diff line Loading @@ -2182,7 +2182,7 @@ static struct clk wkup_32k_fck = { static struct clk gpio1_dbck = { static struct clk gpio1_dbck = { .name = "gpio1_dbck", .name = "gpio1_dbck", .ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2_dflt, .parent = &wkup_32k_fck, .parent = &wkup_32k_fck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, .enable_bit = OMAP3430_EN_GPIO1_SHIFT, Loading Loading @@ -2427,7 +2427,7 @@ static struct clk per_32k_alwon_fck = { static struct clk gpio6_dbck = { static struct clk gpio6_dbck = { .name = "gpio6_dbck", .name = "gpio6_dbck", .ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2_dflt, .parent = &per_32k_alwon_fck, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, .enable_bit = OMAP3430_EN_GPIO6_SHIFT, Loading @@ -2437,7 +2437,7 @@ static struct clk gpio6_dbck = { static struct clk gpio5_dbck = { static struct clk gpio5_dbck = { .name = "gpio5_dbck", .name = "gpio5_dbck", .ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2_dflt, .parent = &per_32k_alwon_fck, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, .enable_bit = OMAP3430_EN_GPIO5_SHIFT, Loading @@ -2447,7 +2447,7 @@ static struct clk gpio5_dbck = { static struct clk gpio4_dbck = { static struct clk gpio4_dbck = { .name = "gpio4_dbck", .name = "gpio4_dbck", .ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2_dflt, .parent = &per_32k_alwon_fck, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, .enable_bit = OMAP3430_EN_GPIO4_SHIFT, Loading @@ -2457,7 +2457,7 @@ static struct clk gpio4_dbck = { static struct clk gpio3_dbck = { static struct clk gpio3_dbck = { .name = "gpio3_dbck", .name = "gpio3_dbck", .ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2_dflt, .parent = &per_32k_alwon_fck, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, .enable_bit = OMAP3430_EN_GPIO3_SHIFT, Loading @@ -2467,7 +2467,7 @@ static struct clk gpio3_dbck = { static struct clk gpio2_dbck = { static struct clk gpio2_dbck = { .name = "gpio2_dbck", .name = "gpio2_dbck", .ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2_dflt, .parent = &per_32k_alwon_fck, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, .enable_bit = OMAP3430_EN_GPIO2_SHIFT, Loading arch/arm/mach-omap2/devices.c +4 −2 Original line number Original line Diff line number Diff line Loading @@ -354,9 +354,11 @@ static void omap_init_mcspi(void) platform_device_register(&omap2_mcspi1); platform_device_register(&omap2_mcspi1); platform_device_register(&omap2_mcspi2); platform_device_register(&omap2_mcspi2); #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) if (cpu_is_omap2430() || cpu_is_omap343x()) platform_device_register(&omap2_mcspi3); platform_device_register(&omap2_mcspi3); #endif #endif #ifdef CONFIG_ARCH_OMAP3 #ifdef CONFIG_ARCH_OMAP3 if (cpu_is_omap343x()) platform_device_register(&omap2_mcspi4); platform_device_register(&omap2_mcspi4); #endif #endif } } Loading arch/arm/mach-omap2/prm-regbits-34xx.h +1 −1 Original line number Original line Diff line number Diff line Loading @@ -409,7 +409,7 @@ /* PM_PREPWSTST_CAM specific bits */ /* PM_PREPWSTST_CAM specific bits */ /* PM_PWSTCTRL_USBHOST specific bits */ /* PM_PWSTCTRL_USBHOST specific bits */ #define OMAP3430ES2_SAVEANDRESTORE_SHIFT (1 << 4) #define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4 /* RM_RSTST_PER specific bits */ /* RM_RSTST_PER specific bits */ Loading Loading
arch/arm/mach-omap2/clock24xx.c +5 −5 Original line number Original line Diff line number Diff line Loading @@ -103,10 +103,10 @@ static struct omap_clk omap24xx_clks[] = { CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), /* DSS domain clocks */ /* DSS domain clocks */ CLK(NULL, "dss_ick", &dss_ick, CK_243X | CK_242X), CLK("omapfb", "ick", &dss_ick, CK_243X | CK_242X), CLK(NULL, "dss1_fck", &dss1_fck, CK_243X | CK_242X), CLK("omapfb", "dss1_fck", &dss1_fck, CK_243X | CK_242X), CLK(NULL, "dss2_fck", &dss2_fck, CK_243X | CK_242X), CLK("omapfb", "dss2_fck", &dss2_fck, CK_243X | CK_242X), CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X | CK_242X), CLK("omapfb", "tv_fck", &dss_54m_fck, CK_243X | CK_242X), /* L3 domain clocks */ /* L3 domain clocks */ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), Loading Loading @@ -206,7 +206,7 @@ static struct omap_clk omap24xx_clks[] = { CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), Loading
arch/arm/mach-omap2/clock34xx.c +6 −6 Original line number Original line Diff line number Diff line Loading @@ -157,7 +157,7 @@ static struct omap_clk omap34xx_clks[] = { CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X), CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X), CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X), CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X), CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X), CLK("musb_hdrc", "ick", &hsotgusb_ick, CK_343X), CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), Loading Loading @@ -197,11 +197,11 @@ static struct omap_clk omap34xx_clks[] = { CLK("omap_rng", "ick", &rng_ick, CK_343X), CLK("omap_rng", "ick", &rng_ick, CK_343X), CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), CLK(NULL, "des1_ick", &des1_ick, CK_343X), CLK(NULL, "des1_ick", &des1_ick, CK_343X), CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X), CLK("omapfb", "dss1_fck", &dss1_alwon_fck, CK_343X), CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X), CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X), CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X), CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X), CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X), CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X), CLK(NULL, "dss_ick", &dss_ick, CK_343X), CLK("omapfb", "ick", &dss_ick, CK_343X), CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), CLK(NULL, "cam_ick", &cam_ick, CK_343X), CLK(NULL, "cam_ick", &cam_ick, CK_343X), CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), Loading
arch/arm/mach-omap2/clock34xx.h +6 −6 Original line number Original line Diff line number Diff line Loading @@ -2182,7 +2182,7 @@ static struct clk wkup_32k_fck = { static struct clk gpio1_dbck = { static struct clk gpio1_dbck = { .name = "gpio1_dbck", .name = "gpio1_dbck", .ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2_dflt, .parent = &wkup_32k_fck, .parent = &wkup_32k_fck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, .enable_bit = OMAP3430_EN_GPIO1_SHIFT, Loading Loading @@ -2427,7 +2427,7 @@ static struct clk per_32k_alwon_fck = { static struct clk gpio6_dbck = { static struct clk gpio6_dbck = { .name = "gpio6_dbck", .name = "gpio6_dbck", .ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2_dflt, .parent = &per_32k_alwon_fck, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, .enable_bit = OMAP3430_EN_GPIO6_SHIFT, Loading @@ -2437,7 +2437,7 @@ static struct clk gpio6_dbck = { static struct clk gpio5_dbck = { static struct clk gpio5_dbck = { .name = "gpio5_dbck", .name = "gpio5_dbck", .ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2_dflt, .parent = &per_32k_alwon_fck, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, .enable_bit = OMAP3430_EN_GPIO5_SHIFT, Loading @@ -2447,7 +2447,7 @@ static struct clk gpio5_dbck = { static struct clk gpio4_dbck = { static struct clk gpio4_dbck = { .name = "gpio4_dbck", .name = "gpio4_dbck", .ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2_dflt, .parent = &per_32k_alwon_fck, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, .enable_bit = OMAP3430_EN_GPIO4_SHIFT, Loading @@ -2457,7 +2457,7 @@ static struct clk gpio4_dbck = { static struct clk gpio3_dbck = { static struct clk gpio3_dbck = { .name = "gpio3_dbck", .name = "gpio3_dbck", .ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2_dflt, .parent = &per_32k_alwon_fck, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, .enable_bit = OMAP3430_EN_GPIO3_SHIFT, Loading @@ -2467,7 +2467,7 @@ static struct clk gpio3_dbck = { static struct clk gpio2_dbck = { static struct clk gpio2_dbck = { .name = "gpio2_dbck", .name = "gpio2_dbck", .ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2_dflt, .parent = &per_32k_alwon_fck, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, .enable_bit = OMAP3430_EN_GPIO2_SHIFT, Loading
arch/arm/mach-omap2/devices.c +4 −2 Original line number Original line Diff line number Diff line Loading @@ -354,9 +354,11 @@ static void omap_init_mcspi(void) platform_device_register(&omap2_mcspi1); platform_device_register(&omap2_mcspi1); platform_device_register(&omap2_mcspi2); platform_device_register(&omap2_mcspi2); #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) if (cpu_is_omap2430() || cpu_is_omap343x()) platform_device_register(&omap2_mcspi3); platform_device_register(&omap2_mcspi3); #endif #endif #ifdef CONFIG_ARCH_OMAP3 #ifdef CONFIG_ARCH_OMAP3 if (cpu_is_omap343x()) platform_device_register(&omap2_mcspi4); platform_device_register(&omap2_mcspi4); #endif #endif } } Loading
arch/arm/mach-omap2/prm-regbits-34xx.h +1 −1 Original line number Original line Diff line number Diff line Loading @@ -409,7 +409,7 @@ /* PM_PREPWSTST_CAM specific bits */ /* PM_PREPWSTST_CAM specific bits */ /* PM_PWSTCTRL_USBHOST specific bits */ /* PM_PWSTCTRL_USBHOST specific bits */ #define OMAP3430ES2_SAVEANDRESTORE_SHIFT (1 << 4) #define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4 /* RM_RSTST_PER specific bits */ /* RM_RSTST_PER specific bits */ Loading