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Commit ca1ee4b2 authored by Dmitry Kravkov's avatar Dmitry Kravkov Committed by David S. Miller
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bnx2x: Add and correct PCI link speed prints 



This adds the print of the PCI gen3 link speed (8GHz), as well as correcting
the same print for 57712 boards (the print erroneously showed a 2.5GHz speed).

Signed-off-by: default avatarDmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: default avatarYuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: default avatarAriel Elior <ariele@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e09b74d0

drivers/net/ethernet/broadcom/bnx2x/bnx2x.h

+5 −0
Original line number Original line Diff line number Diff line
@@ -2342,4 +2342,9 @@ enum { 




#define NUM_MACS	8

#define NUM_MACS	8





enum bnx2x_pci_bus_speed {

	BNX2X_PCI_LINK_SPEED_2500 = 2500,

	BNX2X_PCI_LINK_SPEED_5000 = 5000,

	BNX2X_PCI_LINK_SPEED_8000 = 8000

};

#endif /* bnx2x.h */
 
#endif /* bnx2x.h */

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

+26 −14
Original line number Original line Diff line number Diff line
@@ -12111,15 +12111,26 @@ err_out: 
	return rc;

	return rc;

}

}





static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed)

static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width,

				       enum bnx2x_pci_bus_speed *speed)

{

{

	u32 val = 0;

	u32 link_speed, val = 0;





	pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);

	pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);

	*width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;

	*width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;





	/* return value of 1=2.5GHz 2=5GHz */

	link_speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;

	*speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;



	switch (link_speed) {

	case 3:

		*speed = BNX2X_PCI_LINK_SPEED_8000;

		break;

	case 2:

		*speed = BNX2X_PCI_LINK_SPEED_5000;

		break;

	default:

		*speed = BNX2X_PCI_LINK_SPEED_2500;

	}

}

}





static int bnx2x_check_firmware(struct bnx2x *bp)

static int bnx2x_check_firmware(struct bnx2x *bp)
@@ -12482,7 +12493,8 @@ static int bnx2x_init_one(struct pci_dev *pdev, 
{

{

	struct net_device *dev = NULL;

	struct net_device *dev = NULL;

	struct bnx2x *bp;

	struct bnx2x *bp;

	int pcie_width, pcie_speed;

	int pcie_width;

	enum bnx2x_pci_bus_speed pcie_speed;

	int rc, max_non_def_sbs;

	int rc, max_non_def_sbs;

	int rx_count, tx_count, rss_count, doorbell_size;

	int rx_count, tx_count, rss_count, doorbell_size;

	int max_cos_est;

	int max_cos_est;
@@ -12634,14 +12646,14 @@ static int bnx2x_init_one(struct pci_dev *pdev, 
	BNX2X_DEV_INFO("got pcie width %d and speed %d\n",

	BNX2X_DEV_INFO("got pcie width %d and speed %d\n",

		       pcie_width, pcie_speed);

		       pcie_width, pcie_speed);





	BNX2X_DEV_INFO(

	BNX2X_DEV_INFO("%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",

		"%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",

		       board_info[ent->driver_data].name,

		       board_info[ent->driver_data].name,

		       (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),

		       (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),

		       pcie_width,

		       pcie_width,

		    ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||

		       pcie_speed == BNX2X_PCI_LINK_SPEED_2500 ? "2.5GHz" :

		     (CHIP_IS_E2(bp) && pcie_speed == 1)) ?

		       pcie_speed == BNX2X_PCI_LINK_SPEED_5000 ? "5.0GHz" :

		    "5GHz (Gen2)" : "2.5GHz",

		       pcie_speed == BNX2X_PCI_LINK_SPEED_8000 ? "8.0GHz" :

		       "Unknown",

		       dev->base_addr, bp->pdev->irq, dev->dev_addr);

		       dev->base_addr, bp->pdev->irq, dev->dev_addr);





	return 0;

	return 0;