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Commit c94fa15b authored by Sekhar Nori's avatar Sekhar Nori Committed by Kevin Hilman
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davinci: move PSC register definitions from psc.c to psc.h 



The motivation behind the change is to use the same
definitions in the assembly code responsible for
suspending the SoC, a part of which is to clock gate
the DDR2 clock.

Note that the assembly code cannot invoke the C function
meant for this. The main reason being that stack in DDR2
cannot be accessed while DDR2 clock is being clock gated.

Signed-off-by: default avatarSekhar Nori <nsekhar@ti.com>
Signed-off-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
parent 7ec4b243

arch/arm/mach-davinci/include/mach/psc.h

+11 −0
Original line number Diff line number Diff line
@@ -180,6 +180,17 @@ 
#define DA8XX_LPSC1_CR_P3_SS		26

#define DA8XX_LPSC1_L3_CBA_RAM		31



/* PSC register offsets */

#define EPCPR		0x070

#define PTCMD		0x120

#define PTSTAT		0x128

#define PDSTAT		0x200

#define PDCTL1		0x304

#define MDSTAT		0x800

#define MDCTL		0xA00



#define MDSTAT_STATE_MASK 0x1f



extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);

extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,

		unsigned int id, char enable);

arch/arm/mach-davinci/psc.c

+0 −11
Original line number Diff line number Diff line
@@ -25,17 +25,6 @@ 
#include <mach/cputype.h>

#include <mach/psc.h>



/* PSC register offsets */

#define EPCPR		0x070

#define PTCMD		0x120

#define PTSTAT		0x128

#define PDSTAT		0x200

#define PDCTL1		0x304

#define MDSTAT		0x800

#define MDCTL		0xA00



#define MDSTAT_STATE_MASK 0x1f



/* Return nonzero iff the domain's clock is active */

int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)

{