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Commit c5d0ecc9 authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Jason Cooper
Browse files

ARM: mv78xx0: Move to ID based window creation 



With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.

This will allow to deprecate the name based API, once every
user is removed.

Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: default avatarAndrew Lunn <andrew@lunn.ch>
Tested-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 8baeeeb2

arch/arm/mach-mv78xx0/pcie.c

+11 −12
Original line number Original line Diff line number Diff line
@@ -18,6 +18,11 @@ 
#include <mach/mv78xx0.h>

#include <mach/mv78xx0.h>

#include "common.h"

#include "common.h"





#define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4)

#define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane)   (0xf8 & ~(0x10 << (lane)))

#define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane)  ((port) ? 8 : 4)

#define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane)    (0xf0 & ~(0x10 << (lane)))



struct pcie_port {

struct pcie_port {

	u8			maj;

	u8			maj;

	u8			min;

	u8			min;
@@ -71,7 +76,6 @@ static void __init mv78xx0_pcie_preinit(void) 
	start = MV78XX0_PCIE_MEM_PHYS_BASE;

	start = MV78XX0_PCIE_MEM_PHYS_BASE;

	for (i = 0; i < num_pcie_ports; i++) {

	for (i = 0; i < num_pcie_ports; i++) {

		struct pcie_port *pp = pcie_port + i;

		struct pcie_port *pp = pcie_port + i;

		char winname[MVEBU_MBUS_MAX_WINNAME_SZ];





		snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),

		snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),

			"PCIe %d.%d MEM", pp->maj, pp->min);

			"PCIe %d.%d MEM", pp->maj, pp->min);
@@ -85,17 +89,12 @@ static void __init mv78xx0_pcie_preinit(void) 
		if (request_resource(&iomem_resource, &pp->res))

		if (request_resource(&iomem_resource, &pp->res))

			panic("can't allocate PCIe MEM sub-space");

			panic("can't allocate PCIe MEM sub-space");





		snprintf(winname, sizeof(winname), "pcie%d.%d",

		mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min),

			 pp->maj, pp->min);

					    MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min),



					    pp->res.start, resource_size(&pp->res));

		mvebu_mbus_add_window_remap_flags(winname,

		mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min),

						  pp->res.start,

						  MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min),

						  resource_size(&pp->res),

						  i * SZ_64K, SZ_64K, 0);

						  MVEBU_MBUS_NO_REMAP,

						  MVEBU_MBUS_PCI_MEM);

		mvebu_mbus_add_window_remap_flags(winname,

						  i * SZ_64K, SZ_64K,

						  0, MVEBU_MBUS_PCI_IO);

	}

	}

}

}