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Commit c4c71355 authored by Sachin Kamat's avatar Sachin Kamat Committed by Kukjin Kim
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ARM: EXYNOS: Update HSOTG PHY clock setting for EXYNOS4X12 



Adds clock setting entries for EXYNOS4212 and EXYNOS4412 platforms.

Signed-off-by: default avatarSachin Kamat <sachin.kamat@linaro.org>
[fixed compilation warning which is reported by Arnd Bergmann]
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 7d896aac

arch/arm/mach-exynos/include/mach/regs-usb-phy.h

+15 −5
Original line number Diff line number Diff line
@@ -35,11 +35,21 @@ 
#define PHY1_COMMON_ON_N		(1 << 7)

#define PHY0_COMMON_ON_N		(1 << 4)

#define PHY0_ID_PULLUP			(1 << 2)

#define CLKSEL_MASK			(0x3 << 0)

#define CLKSEL_SHIFT			(0)

#define CLKSEL_48M			(0x0 << 0)

#define CLKSEL_12M			(0x2 << 0)

#define CLKSEL_24M			(0x3 << 0)



#define EXYNOS4_CLKSEL_SHIFT		(0)



#define EXYNOS4210_CLKSEL_MASK		(0x3 << 0)

#define EXYNOS4210_CLKSEL_48M		(0x0 << 0)

#define EXYNOS4210_CLKSEL_12M		(0x2 << 0)

#define EXYNOS4210_CLKSEL_24M		(0x3 << 0)



#define EXYNOS4X12_CLKSEL_MASK		(0x7 << 0)

#define EXYNOS4X12_CLKSEL_9600K		(0x0 << 0)

#define EXYNOS4X12_CLKSEL_10M		(0x1 << 0)

#define EXYNOS4X12_CLKSEL_12M		(0x2 << 0)

#define EXYNOS4X12_CLKSEL_19200K	(0x3 << 0)

#define EXYNOS4X12_CLKSEL_20M		(0x4 << 0)

#define EXYNOS4X12_CLKSEL_24M		(0x5 << 0)



#define EXYNOS4_RSTCON			EXYNOS4_HSOTG_PHYREG(0x08)

#define HOST_LINK_PORT_SWRST_MASK	(0xf << 6)

arch/arm/mach-exynos/setup-usb-phy.c

+44 −16
Original line number Diff line number Diff line
@@ -31,27 +31,55 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev) 
	struct clk *xusbxti_clk;

	u32 phyclk;



	/* set clock frequency for PLL */

	phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;



	xusbxti_clk = clk_get(&pdev->dev, "xusbxti");

	if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {

		if (soc_is_exynos4210()) {

			/* set clock frequency for PLL */

			phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;



			switch (clk_get_rate(xusbxti_clk)) {

			case 12 * MHZ:

			phyclk |= CLKSEL_12M;

				phyclk |= EXYNOS4210_CLKSEL_12M;

				break;

			case 48 * MHZ:

				phyclk |= EXYNOS4210_CLKSEL_48M;

				break;

			default:

			case 24 * MHZ:

			phyclk |= CLKSEL_24M;

				phyclk |= EXYNOS4210_CLKSEL_24M;

				break;

			}

			writel(phyclk, EXYNOS4_PHYCLK);

		} else if (soc_is_exynos4212() || soc_is_exynos4412()) {

			/* set clock frequency for PLL */

			phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;



			switch (clk_get_rate(xusbxti_clk)) {

			case 9600 * KHZ:

				phyclk |= EXYNOS4X12_CLKSEL_9600K;

				break;

			case 10 * MHZ:

				phyclk |= EXYNOS4X12_CLKSEL_10M;

				break;

			case 12 * MHZ:

				phyclk |= EXYNOS4X12_CLKSEL_12M;

				break;

			case 19200 * KHZ:

				phyclk |= EXYNOS4X12_CLKSEL_19200K;

				break;

			case 20 * MHZ:

				phyclk |= EXYNOS4X12_CLKSEL_20M;

				break;

			default:

		case 48 * MHZ:

			case 24 * MHZ:

				/* default reference clock */

				phyclk |= EXYNOS4X12_CLKSEL_24M;

				break;

			}

			writel(phyclk, EXYNOS4_PHYCLK);

		}

		clk_put(xusbxti_clk);

	}



	writel(phyclk, EXYNOS4_PHYCLK);

}



static int exynos4210_usb_phy0_init(struct platform_device *pdev)

arch/arm/plat-samsung/include/plat/cpu.h

+4 −0
Original line number Diff line number Diff line
@@ -132,6 +132,10 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) 


#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }



#ifndef KHZ

#define KHZ (1000)

#endif



#ifndef MHZ

#define MHZ (1000*1000)

#endif