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Commit c4aed353 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC fixes from Arnd Bergmann:
 "Small fixes on multiple ARM platforms
   - A build regression from a previous fix on dove and mv78xx0
   - Two fixes for recently (3.5-rc1) changed mmp/pxa code
   - multiple omap2+ bug fixes
   - two trivial fixes for i.MX
   - one v3.5 regression for mxs"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: apx4devkit: fix FEC enabling PHY clock
  ARM: OMAP2+: hwmod data: Fix wrong McBSP clock alias on OMAP4
  ARM: OMAP4: hwmod data: temporarily comment out data for the usb_host_fs and aess IP blocks
  ARM: Orion: Fix WDT compile for Dove and MV78xx0
  ARM: mmp: remove mach/gpio-pxa.h
  ARM: imx: assert SCC gate stays enabled
  ARM: OMAP4: TWL6030: ensure sys_nirq1 is mux'd and wakeup enabled
  ARM: OMAP2: Overo: init I2C before MMC to fix MMC suspend/resume failure
  ARM: imx27_visstrim_m10: Do not include <asm/system.h>
  ARM: pxa: hx4700: Fix basic suspend/resume
parents 6bc51545 e15ebe05

arch/arm/mach-dove/include/mach/bridge-regs.h

+1 −0
Original line number Diff line number Diff line
@@ -50,5 +50,6 @@ 
#define POWER_MANAGEMENT	(BRIDGE_VIRT_BASE | 0x011c)



#define TIMER_VIRT_BASE		(BRIDGE_VIRT_BASE | 0x0300)

#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)



#endif

arch/arm/mach-dove/include/mach/dove.h

+1 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ 


/* North-South Bridge */

#define BRIDGE_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0x20000)

#define BRIDGE_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x20000)



/* Cryptographic Engine */

#define DOVE_CRYPT_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x30000)

arch/arm/mach-imx/clk-imx35.c

+8 −1
Original line number Diff line number Diff line
@@ -201,7 +201,6 @@ int __init mx35_clocks_init() 
			pr_err("i.MX35 clk %d: register failed with %ld\n",

				i, PTR_ERR(clk[i]));





	clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");

	clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");

	clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
@@ -264,6 +263,14 @@ int __init mx35_clocks_init() 
	clk_prepare_enable(clk[iim_gate]);

	clk_prepare_enable(clk[emi_gate]);



	/*

	 * SCC is needed to boot via mmc after a watchdog reset. The clock code

	 * before conversion to common clk also enabled UART1 (which isn't

	 * handled here and not needed for mmc) and IIM (which is enabled

	 * unconditionally above).

	 */

	clk_prepare_enable(clk[scc_gate]);



	imx_print_silicon_rev("i.MX35", mx35_revision());



#ifdef CONFIG_MXC_USE_EPIT

arch/arm/mach-imx/mach-imx27_visstrim_m10.c

+1 −1
Original line number Diff line number Diff line
@@ -38,7 +38,7 @@ 
#include <asm/mach-types.h>

#include <asm/mach/arch.h>

#include <asm/mach/time.h>

#include <asm/system.h>

#include <asm/system_info.h>

#include <mach/common.h>

#include <mach/iomux-mx27.h>

arch/arm/mach-mmp/include/mach/gpio-pxa.h

deleted100644 → 0
+0 −29
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#ifndef __ASM_MACH_GPIO_PXA_H

#define __ASM_MACH_GPIO_PXA_H



#include <mach/addr-map.h>

#include <mach/cputype.h>

#include <mach/irqs.h>



#define GPIO_REGS_VIRT	(APB_VIRT_BASE + 0x19000)



#define BANK_OFF(n)	(((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))

#define GPIO_REG(x)	(*(volatile u32 *)(GPIO_REGS_VIRT + (x)))



#define gpio_to_bank(gpio)	((gpio) >> 5)



/* NOTE: these macros are defined here to make optimization of

 * gpio_{get,set}_value() to work when 'gpio' is a constant.

 * Usage of these macros otherwise is no longer recommended,

 * use generic GPIO API whenever possible.

 */

#define GPIO_bit(gpio)	(1 << ((gpio) & 0x1f))



#define GPLR(x)		GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x00)

#define GPDR(x)		GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x0c)

#define GPSR(x)		GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x18)

#define GPCR(x)		GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x24)



#include <plat/gpio-pxa.h>



#endif /* __ASM_MACH_GPIO_PXA_H */